Method and apparatus for adjusting DRAM signal timings

An apparatus comprising:

• a memory controller generating a clock signal and at least one command signal, wherein the memory controller further comprises logic to selectively delay the clock signal by a controllable degree;
• a memory device;
• and
• a plurality of conductors coupling the memory controller to the memory device, and through which the clock signal and the at least one command signal are transmitted.

A computer system comprising:

• a processor;
• a memory controller coupled to the processor and generating a clock signal and at least one command signal, wherein the memory controller further comprises logic to selectively delay the clock signal by a controllable degree;
• a memory device;
• and
• a plurality of conductors coupling the memory controller to the memory device, and through which the clock signal and the at least one command signal are transmitted.

A computer readable medium comprising instructions, which when executed by a processor, causes the processor to:

• access a memory controller to which the processor is coupled;
• set a degree to which a clock signal generated by the memory controller is delayed such that the transitions of the clock signal as received by a memory device are delayed;
• cause the memory controller to begin transmitting at least one command signal to a memory device to which the memory controller is coupled;
• and
• cause the memory controller to transmit the clock signal with at least one transition in the clock signal being timed to occur after the beginning of the transmission of the at least one command signal to the memory device, wherein the position of the at least one transition in the clock signal relative to the beginning of the transmission of the at least one command signal to the memory device is adjusted based on the setting of the degree to which the clock signal is delayed.