Pre-fetch control device, data processing apparatus and pre-fetch control method

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a request address register storing a request address based on a request for access to the cache memory;
• a primary cache-miss address register storing an address value in the request address register;
• a first calculator adding a specific value to the address value of the primary cache-miss address register and outputting the result;
• a pre-fetch address queue with a plurality of entries each storing an address value as an entry address, comparing the request address of the request address register with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address;
• a read register storing output of the pre-fetch address queue;
• a second calculator adding the specific value to the entry address of the read register and outputting the result;
• and
• a registration unit registering outputs of the first and second calculators in one of the plurality of entries of the pre-fetch address queue as an entry address.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a request address register storing a request address based on a request for access to the cache memory;
• a primary cache-miss address register storing an address value of the request address register;
• a first calculator adding/subtracting a specific value to/from the address value of the primary cache-miss address register, according to instructions and outputting the added/subtracted address value;
• a pre-fetch address queue with a plurality of entries each storing an address value as an entry address together with a direction flag indicating a pre-fetching direction, comparing the request address of the request address register with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the direction flag;
• a read register storing output of the pre-fetch address queue;
• a second calculator adding/subtracting the specific value to the entry address of the read register, based on a value of the direction flag and outputting the result;
• a first registration unit instructing the first calculator to add a value and registering the output of the first calculator as an entry address in one of the plurality of entries together with the direction flag indicating an ascending pre-fetching direction, and simultaneously instructing the first calculator to subtract a value and registering output of the first calculator as an entry address in one of the plurality of entries together with the direction flag indicating a descending pre-fetching direction;
• and
• a second registration unit registering output of the second calculator in one of the plurality of entries as the entry address together with a direction flag of the read register.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a request address register storing a request address based on a request for an access to the cache memory;
• a primary cache-miss address register storing an address value of the request address register;
• a first calculator adding/subtracting a specific value to/from the address value of the primary cache-miss address register, according to instructions and outputting the result;
• a pre-fetch address queue with a plurality of entries each storing the address value as an entry address together with difference value information indicating the difference between the request address and a pre-fetch address designating a pre-fetching position, a counter value and a direction flag indicating a pre-fetching direction, comparing a request address of the request address register with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the difference information, the counter value and the direction flag;
• a read register storing output of the request address queue;
• a second calculator adding/subtracting a specific value to/from the entry address of the read register, based on the value of the direction flag;
• counter value calculation unit for decrementing a counter value of the read register, and outputting an initial value as a counter value if the counter value becomes a specific value and outputting the decremented value as a counter value if the counter value does not become the specific value;
• a difference information determination unit modifying and outputting difference information of the read register according to a predetermined rule if the counter value of the read register is the specific value, and outputting the difference information of the read register without modifications if the counter value is not the specific value;
• a pre-fetch address calculation unit for calculating the pre-fetch address, based on the difference information, the direction flag and the address value of the read register;
• a first registration unit instructing the first calculator to add a value and registering the counter value set to the initial value, the difference value and output of the first calculator in one of the plurality of entries as an entry address together with a direction flag indicating an ascending pre-fetching direction, and simultaneously instructing the first calculator to subtract a value and registering the counter value set to the initial value, the difference value and output of the first calculator in one of the plurality of entries as an entry address together with a direction flag indicating a descending pre-fetching direction;
• and
• a second registration unit registering the counter value output from the counter value calculation unit, the difference value output from the difference information determination unit, and output of the second calculator in one of the plurality of entries as the entry address together with the direction flag of the read register.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a request address register storing a request address based on a request for access to the cache memory together with first type information indicating whether the request address is for a write request;
• a primary cache-miss address register storing the address value and first type information of the request address register;
• a first calculator adding a specific value to the address value of the primary cache-miss address register and outputting the result;
• a pre-fetch address queue with a plurality of entries each storing an address value as an entry address together with the first type information, comparing the request address of the request address register with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the first type information;
• a read register storing output of the pre-fetch address queue;
• a second calculator adding the specific value to the entry address of the read register and outputting the result;
• a predictor determining second type information indicating whether a pre-fetch request is for a write pre-fetch request, based on the first type information of the read register and the first type information of the request address register;
• and
• a registration unit registering the output of the first calculator and the first type information of the first cache-miss address register, and the output of the second calculator and the second type information output from the predictor in one of the plurality of entries of the pre-fetch address queue, as the entry address and the first type information, respectively.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a plurality of request address registers each storing a request address based on a request for access to the cache memory;
• a selector selecting and outputting one of respective request addresses of the plurality of request address registers;
• a primary cache-miss address register storing an address output from the selector;
• a first calculator adding a specific value to the address value of the primary cache-miss address register and outputting the result;
• a pre-fetch address queue with a plurality of entries each storing an address value as an entry address, comparing the respective request addresses of the plurality of request address registers with respective entry addresses of the plurality of entries, and if a request address and an entry address are the same, outputting the entry address;
• a read register storing output of the pre-fetch address queue;
• a second calculator adding the specific value to the entry address of the read register and outputting the result;
• a pre-fetch address register storing output of the second calculator;
• and
• a registration unit registering the outputs of the first and second calculators in one of the plurality of entries of the pre-fetch address queue as pre-fetch address.

A data processing apparatus, comprising;

• cache memory means;
• address registration means for registering an address value based on an address using which a memory is previously accessed;
• and
• pre-fetch request means for requesting the cache memory means to pre-fetch data, based on a result of comparison a request address using which access was requested and the address value registered in the address registration means.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• request address register means for storing a request address based on a request for an access to the cache memory;
• primary cache-miss address register means for storing an address value of the request address register means;
• first calculator means for adding a specific value to the address value of the primary cache-miss address register means and outputting the result;
• pre-fetch address queue means with a plurality of entries each storing an address value as an entry address, comparing the request address of the request address register means with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address;
• read register means for storing output of the pre-fetch address queue means;
• second calculator means for adding the specific value to the entry address of the read register means and outputting the result;
• and
• registration means for registering outputs of the first and second calculator means in one of the plurality of entries of the pre-fetch address queue means as an entry address.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• request address register means for storing a request address based on a request for an access to the cache memory;
• primary cache-miss address register means for storing an address value of the request address register means;
• first calculator means for adding/subtracting a specific value to/from the address value of the primary cache-miss address register means, according to instructions and outputting the result;
• pre-fetch address queue means with a plurality of entries each storing an address value as an entry address together with a direction flag indicating pre-fetching direction, comparing the request address of the request address register means with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the direction flag;
• read register means storing output of the pre-fetch address queue means;
• second calculator means for adding/subtracting the specific value to the entry address of the read register means, based on a value of the direction flag and outputting the result;
• first registration means for instructing the first calculator means to add a value and registering the output of the first calculator means as an entry address in one of the plurality of entries together with the direction flag indicating an ascending pre-fetching direction, and simultaneously instructing the first calculator means to subtract a value and registering output of the first calculator means as an entry address in one of the plurality of entries together with the direction flag indicating a descending pre-fetching direction;
• and
• second registration means for registering output of the second calculator means in one of the plurality of entries as an entry address together with the direction flag of the read register means.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• request address register means for storing a request address based on a request for an access to the cache memory;
• primary cache-miss address register means for storing an address value of the request address register means;
• first calculator means for adding/subtracting a specific value to/from the address value of the primary cache-miss address register means, according to instructions and outputting the result;
• pre-fetch address queue means with a plurality of entries each storing an address value as an entry address together with the difference value information indicating difference between the request address and a pre-fetch address designating a pre-fetching position, a counter value and a direction flag indicating a pre-fetching direction, comparing a request address of the request address register means with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the difference information, the counter value and the direction flag;
• read register means storing output of the request address queue means;
• second calculator means adding/subtracting a specific value to/from the entry address of the read register means, based on a value of the direction flag;
• counter value calculation means for decrementing a counter value of the read register means, and outputting an initial value as a counter value if the counter value becomes a specific value and outputting the decremented value as a counter value if the counter value does not become the specific value;
• difference information determination means for modifying and outputting difference information of the read register means according to a predetermined rule if the counter value of the read register means is the specific value, and outputting the difference information of the read register means without modifications if the counter value is not the specific value;
• pre-fetch address calculation means for calculating the pre-fetch address, based on the difference information, the direction flag and the address value of the read register means;
• first registration means for instructing the first calculator means to add a value and registering the counter value set to the initial value, the difference value and output of the first calculator means in one of the plurality of entries as an entry address together with a direction flag indicating an ascending pre-fetching direction, and simultaneously instructing the first calculator means to subtract a value and registering the counter value set to the initial value, the difference value and output of the first calculator means in one of the plurality of entries as an entry address together with a direction flag indicating a descending pre-fetching direction;
• and
• second registration means for registering the counter value output from the counter value calculation means, the difference value output from the difference information determination means and output of the second calculator means in one of the plurality of entries as the entry address together with the direction flag of the read register means.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• request address register means for storing a request address based on a request for an access to the cache memory together with first type information indicating whether the request address is for a write request;
• primary cache-miss address register means for storing the address value and first type information of the request address register means;
• first calculator means for adding a specific value to the address value of the primary cache-miss address register means and outputting the result;
• pre-fetch address queue means with a plurality of entries each storing an address value as an entry address together with the first type information, comparing the request address of the request address register means with respective entry addresses of the plurality of entries, and if the request address and an entry address are the same, outputting the entry address together with the first type information;
• read register means storing output of the pre-fetch address queue means;
• second calculator means for adding the specific value to the entry address of the read register means and outputting the result;
• predictor means for determining second type information indicating whether a pre-fetch request is for a write pre-fetch request, based on the first type information of the read register means and the first type information of the request address register means;
• and
• registration means for registering the output of the first calculator means and the first type information of the first cache-miss address register means, and the output of the second calculator means and the second type information output from the predictor means in one of the plurality of entries of the pre-fetch address queue means, as the entry address and the first type information, respectively.

A pre-fetch control device that is used in a data processing apparatus with a cache memory, comprising:

• a plurality of request address register means each for storing a request address based on a request for an access to the cache memory;
• selector means for selecting and outputting one of respective request addresses of the plurality of request address register means;
• primary cache-miss address register means for storing an address output from the selector means;
• first calculator means for adding a specific value to the address value of the primary cache-miss address register means and outputting the added address value;
• pre-fetch address queue means with a plurality of entries each storing an address value as an entry address, comparing the respective request addresses of the plurality of request address register means with respective entry addresses of the plurality of entries, and if an request address and an entry address are the same, outputting the entry address;
• read register means for storing output of the pre-fetch address queue means;
• second calculator means adding the specific value to the entry address of the read register means and outputting the result;
• pre-fetch address register means for storing output of the second calculator means;
• and
• registration means for registering the outputs of the first and second calculator means in one of the plurality of entries of the pre-fetch address queue means as the pre-fetch address.