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US 2004/0003165 A1Published application
Memory subsystem including error correction
OwnerJurgen M. Schulz, Robert E. Cypher +2inventors
InventorsJurgen M. Schulz, Robert E. Cypher, Drew G. Doblar, Emrys Williams
Life of this patent
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Abstract
A memory subsystem including error correction. A memory subsystem includes a memory controller and system memory including a plurality of memory modules. The system memory may be coupled to the memory controller by a memory interconnect. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The memory controller may store portions of a data segment across at least two of the memory modules. The memory controller may further store parity of the portions of the data segment in a corresponding location of another of the memory modules.
Claims31
A memory subsystem comprising:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to store portions of a data segment across at least two of said memory modules;
- and
- wherein said memory controller is further configured to store parity of said portions of said data segment in a corresponding location of another of said memory modules.
6 more elements
A memory subsystem comprising:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to store respective portions of a data segment across at least two of said memory modules;
- and
- wherein said memory controller is further configured to store parity of at least some of said respective portions of said data segment in a corresponding location of another of said memory modules.
6 more elements
A memory subsystem comprising:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to access said system memory in a plurality of slices, each slice including at least one memory module;
- and
- wherein said memory controller is configured to store parity of at least some of said plurality of slices in at least one additional slice.
6 more elements
A computer system comprising:
- a processor configured to execute instructions;
- a memory subsystem coupled to said processor via a system bus, wherein said memory subsystem includes:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to store portions of a data segment across at least two of said memory modules;
- and
- wherein said memory controller is further configured to store parity of said portions of said data segment in a corresponding location of another of said memory modules.
8 more elements
A computer system comprising:
- a processor configured to execute instructions;
- a memory subsystem coupled to said processor via a system bus, wherein said memory subsystem includes:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to store respective portions of a data segment across at least two of said memory modules;
- and
- wherein said memory controller is further configured to store parity of at least some of said respective portions of said data segment in a corresponding location of another of said memory modules.
8 more elements
A computer system comprising:
- a processor configured to execute instructions;
- a memory subsystem coupled to said processor via a system bus, wherein said memory subsystem includes:
- a memory controller;
- a system memory coupled to said memory controller via a memory interconnect;
- wherein said system memory includes a plurality of memory modules each including:
- a circuit board;
- and
- a plurality of memory chips mounted to said circuit board;
- wherein said memory controller is configured to access said system memory in a plurality of slices, each slice including at least one memory module;
- and
- wherein said memory controller is configured to store parity of at least some of said plurality of slices in at least one additional slice.
8 more elements
Dependencies are inferred from the claim text.