High-speed chip-to-chip communication interface with signal trace routing and phase offset detection

A system comprising:

• an interconnect bus having a plurality of signal traces;
• a first integrated circuit having:
• a transmitter controller, a transmitter interface circuit coupled to the transmitter controller to receive first data synchronously with a system clock signal, to generate a bus clock signal, to convert the first data into second data synchronous with transitions of the bus clock signal and to output the second data to the interconnect bus;
• and
• a second integrated circuit having:
• a receiver controller configured to generate control signals indicative of a phase offset between a rising transition of the bus clock signal and a rising transition of the system clock signal from the second data, and
• a receiver interface circuit coupled to the interconnect bus to retrieve the second data and configured to restore the first data according to the control signals.

A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:

• upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a bit-lane correspondence of the interconnect bus;
• transmitting data from the first integrated circuit to the second integrated across the interconnect bus;
• and
• reconstructing the data at the second integrated circuit according to the deduced bit-lane correspondence.

A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:

• upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit;
• transmitting data from the first integrated circuit to the second integrated across the interconnect bus;
• and
• reconstructing the data at the second integrated circuit according to the deduced phase offset.

An integrated circuit, comprising:

• means for coupling to another integrated circuit via an interconnect bus;
• means for deducing a bit-lane correspondence of the interconnect bus;
• means for receiving data from the other integrated circuit via the interconnect bus;
• and
• means for reconstructing data transmitted by the other integrated circuit according to the deduced bit-lane correspondence.