Method and apparatus for communicating information between lock stepped processors

A method for communication between processors operating in lock step, comprising:

• receiving a read instruction;
• determining a processor address associated with the read instruction;
• determining one or more bits associated with the processor address;
• comparing the determined one or more bits to the processor address to determine a location from which the read instruction is executed;
• and
• reading data from the determined location.

An apparatus for communication between lock step processors, comprising:

• a first communication bus for a first processor;
• a lock step logic coupled to the first communication bus;
• a second communication bus for a second processor, the second communication bus coupled to the lock step logic, wherein the first and the second processors operate in lock step;
• and
• means for communicating between the first and the second processors using the first and the second communications buses without causing a loss of lock step.