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US 2004/0003017 A1Published application
Method for performing complex number multiplication and fast fourier
OwnerAmit Dagan, Gad S. Sheafferinventors
Life of this patent
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Abstract
Multiplication of complex numbers is performed utilizing a single adder. A “mult_i” instruction includes a first subinstruction to perform a multiplication by +i to perform a first portion of a complex multiplication. Next, a second subinstruction calls a multiplication by −i, and the same adder is used to write results to an output register. The output register contains the results of the complex multiplication.
Claims24
A method comprising:
- accessing a value indicative of a coefficient of one of a real or imaginary component of a complex number;
- negating the value in an arithmetic unit;
- and writing the negated value to a location indicative of the other of the real or imaginary component.
A machine-readable medium that provides instructions which when executed by a processor causes said processor to perform operations comprising:
- accessing a value indicative of a coefficient of one of a real or imaginary component of a complex number;
- negating the value in an arithmetic unit;
- and writing the negated value to a location indicative of the other of the real or imaginary component.
A processor comprising:
- a complex number input buffer register to store a real component of a complex number in a first location and an imaginary component of the complex number in a second location, an arithmetic unit to negate a component and a complex number output buffer register comprising a first location for storing a real component of a complex number and a second location for storing an imaginary component of a complex number, said arithmetic unit being connectable between said input buffer register and said output buffer register to negate a value from a first or second location of the input buffer register and write to the second or first location respectively of the output buffer register.
Dependencies are inferred from the claim text.