Voice recognition device, observation probability calculating device, complex fast fourier transform calculation device and method, cache device, and method of controlling the cache device

An observation probability calculation device for use in a voice recognition device, the observation probability calculation device for calculating probabilities that phonemes of a predetermined word can be each observed upon voice recognition, the observation probability calculation device comprising:

• a memory for storing a mean of parameters extracted from phoneme samples and a distribution degree (1/σ) of the mean, wherein the distribution degree is a precision;
• a subtractor for calculating the difference between the mean received from the memory and a feature extracted from a voice signal to be recognized;
• and
• a multiplier for multiplying an output of the subtractor by the distribution degree received from the external memory.

A complex FFT (fast Fourier transform) calculation device which computes a complex FFT of first complex data composed of a first real number and a first imaginary number and a complex FFT of second complex data composed of a second real number and a second imaginary number, the complex FFT calculation device comprising:

• first and second input registers for loading the first and second real numbers and the first and second imaginary numbers;
• first and second coefficient registers for loading a sine coefficient and a cosine coefficient, respectively;
• an adder and a subtractor for operating an addition and a subtraction, respectively, with respect to the values stored in the first and second input registers;
• first and second multipliers for multiplying the output of the subtractor by the output of the first coefficient register and the output of the subtractor by the output of the second coefficient register, respectively;
• first and second storage registers for storing the output of the first multiplier and third and fourth storage registers for storing the output of the second multiplier;
• first and second multiplexers for controlling paths of the outputs of the first through fourth storage registers provided to the adder and the subtractor, respectively;
• an output register for storing the result of the FFT calculation;
• a third multiplexer for providing one of the output of the adder and the output of the subtractor to the output register;
• and
• a controller for controlling selection operations of the first through third multiplexers, the addition operation of the adder, the subtraction operation of the subtractor, the multiplication operation of the multiplier, and the storage operations of the first through fourth storage registers.

A method of calculating a complex (fast Fourier transform) FFT of first complex data composed of a first real number and a first imaginary number and a complex FFT of second complex data composed of a second real number and a second imaginary number, the method comprising the steps of:

• (a) loading a sine coefficient and a cosine coefficient in first and second coefficient registers, respectively, via first and second read buses, respectively;
• (b) loading the first real number in a first input register via the first read bus, loading the second real number in a second input register via the second read bus, calculating a difference between the first and second real numbers using a subtractor, multiplying the output of the subtractor by the sine coefficient of the first coefficient register, storing the result of the multiplication in a first storage register, multiplying the output of the subtractor by the cosine coefficient of the second coefficient register, and storing the result of the multiplication in a second storage register;
• (c) loading the first imaginary number in the first input register via the first read bus, loading the second imaginary number in second input register via the second read bus, calculating a difference between the first and second imaginary numbers using the subtractor, multiplying the output of the subtractor by the sine coefficient of the first coefficient register, storing the result of the multiplication in a third storage register, multiplying the output of the subtractor by the cosine coefficient of the second coefficient register, and storing the result of the multiplication in a fourth storage register;
• (d) calculating a difference between the value stored in the second storage register and the value stored in the third storage register using the subtractor to obtain a real number part of a complex FFT and storing the real number part in an output register;
• and
• (e) calculating a sum of the value stored in the first storage register and the value stored in the fourth storage register using the adder to obtain an imaginary number part of a complex FFT and storing the imaginary number part in the output register.

A recording medium which stores a computer program for calculating a complex FFT of first complex data composed of a first real number and a first imaginary number and a complex FFT of second complex data composed of a second real number and a second imaginary number, the computer program comprising the steps of:

• (a) loading a sine coefficient and a cosine coefficient in first and second coefficient registers, respectively, via first and second read buses, respectively;
• (b) loading the first real number in a first input register via the first read bus, loading the second real number in second input register via the second read bus, calculating a difference between the first and second real numbers using a subtractor, multiplying the output of the subtractor by the sine coefficient of the first coefficient register, storing the result of the multiplication in a first storage register, multiplying the output of the subtractor by the cosine coefficient of the second coefficient register, and storing the result of the multiplication in a second storage register;
• (c) loading the first imaginary number in the first input register via the first read bus, loading the second imaginary number in the second input register via the second read bus, calculating a difference between the first and second imaginary numbers using the subtractor, multiplying the output of the subtractor by the sine coefficient of the first coefficient register, storing the result of the multiplication in a third storage register, multiplying the output of the subtractor by the cosine coefficient of the second coefficient register, and storing the result of the multiplication in a fourth storage register;
• (d) calculating a difference between the value stored in the second storage register and the value stored in the third storage register using the subtractor to obtain a real number part of a complex FFT and storing the real number part in an output register;
• and
• (e) calculating a sum of the value stored in the first storage register and the value stored in the fourth storage register using the adder to obtain an imaginary number part of a complex FFT and storing the imaginary number part in the output register.

A cache which reads a series of data expected to be required next by a central processing unit from an external memory, stores the data, and is primarily accessed before the central processing unit accesses the external memory, the cache comprising:

• an internal memory for storing data stored in the external memory and addresses of the data stored in the external memory;
• a comparator for comparing external addresses used to access the external memory with the external addresses stored in the internal memory to generate an equivalence detection signal that represents either equivalence or nonequivalence;
• an address converter for generating an internal address used to access the internal memory, on the basis of the external address used to access the external memory, a write address received from a command word storage controller, and an upper address of each of the external addresses and for generating an internal memory read/write control signal;
• and
• the command word storage controller for controlling data stored in the external memory to be loaded in the internal memory, wherein the control is made voluntarily or in response to a command received from outside of the cache.

A system comprising:

• a main memory for loading a program necessary to operate the system and a cache control program;
• a central processing unit for controlling the operation of the system according to the program stored in the main memory;
• and
• a cache for reading a series of data expected to be required next by the central processing unit from the main memory, storing the series of data, and being accessed before the main memory is accessed by the central processing unit, the cache comprising:
• an internal memory for storing data stored in the main memory and addresses of the data stored in the main memory;
• a comparator for comparing external addresses used to access the main memory with the external addresses stored in the internal memory to generate an equivalence detection signal that represents either equivalence or nonequivalence;
• an address converter for generating an internal address used to access the internal memory, on the basis of the external address used to access the main memory, a write address received from a command word storage controller, and an upper address of each of the external addresses and for generating an internal memory read/write control signal;
• and
• the command word storage controller for controlling data stored in the main memory to be loaded in the internal memory, wherein the control is made voluntarily or in response to a command received from outside of the cache.

A cache controlling method of a cache which reads a series of data expected to be required next by a central processing unit from an external memory, stores the series of data, and is accessed before the external memory is accessed by the central processing unit, the method comprising the steps of:

• setting an updating pointer for pointing to an arbitrary area of an internal memory of the cache;
• setting a value of the updating pointer by calculating a block to be exchanged with a block of the external memory from the internal memory of the cache;
• and
• exchanging the internal memory of the cache with the external memory on a block-by-block basis starting from the area of the internal memory pointed to by the updating pointer.