US 2004/0002846 A1 · Transistor level verilog

Abstract

A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syntax, associated with the circuit, can be converted directly from Verilog syntax to a SPICE netlist. The SPICE netlist can be used to simulate the timing and other parameters of the circuit. The Verilog syntax can be used to verify that the circuit as built. Also included are a computer readable medium including an instruction set for the above method, and a data structure necessary to carry out the above method.

Claims28

Dependent claims

A method comprising:

inputting a plurality of commands having a syntax language wherein each command includes a first specification and a second specification;
executing a logic simulation controlled by the first specification and ignoring the second specification in the logic simulation;
and
executing a timing simulation controlled by the second specification and ignoring the first specification in the timing simulation.

1 more element

Dependencies are inferred from the claim text.

Transistor level verilog

Life of this patent

Transistor level verilog

Life of this patent

Abstract

Claims28