Harmonic boost signals in up/down direct/super heterodyne conversions for advanced receiver/transmitter architecture

Abstract

A harmonic boosting technique for achieving higher overall system performance is described here. The technique is applicable to devices such as converter, combiner, synthesizer, and voltage control oscillator. A converter has anti-parallel diode pair (hereafter called APDP) cell or a modified Gilbert cell circuit for mixing an input signal with local oscillator (hereinafter called LO). A combiner has a combining circuit to combine even harmonics from LO. A synthesizer has a digitally synthesized network or a multiplier circuit for producing the even harmonics. A voltage control oscillator (hereafter called VCO) has a voltage control circuit for generating very low base frequencies. The principle object of this invention is to demonstrate that a harmonic boosting technique is capable of reducing LO power and frequency thus providing necessary solutions for achieving SOC chipset commercialization. In addition to the compact size, the SOC process using this technique will have lower cost, lower internal interference, lower power consumption and high lineraity.

Dependencies are inferred from the claim text.