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US 2004/0002207 A1Published application
Method of ultra low-k device fabrication
AssigneeCabot Microelectronics Corporation
InventorChris C. Yu
Life of this patent
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Abstract
A method for fabricating a region of low dielectric constant between metal layers of a substrate, such as an integrated circuit, that eliminate or minimize the problems associated with the existing and future low-k materials and processes. The method utilizes a sacrificial layer or an ultra low-k layer to form a major, but not entire, portion of the dielectric layer between the metal layers, using innovative integration schemes and CMP processes.
Claims57
A method for fabricating an integrated circuit having an ultra low-k region, comprising the steps of:
- a) forming a substrate having a first material layer;
- b) patterning the first material layer to form a plurality of features each having a top surface and to form gaps between the features;
- c) depositing a first oxide material layer onto the top surface of the features and into the gaps;
- d) depositing a first sacrificial material layer onto the first oxide layer;
- e) polishing the first sacrificial layer to form a co-planar surface comprising the first sacrificial layer and the first oxide layer on the top surface of the features, wherein sacrificial material remains in the gaps;
- f) depositing a second oxide layer onto the co-planar surface;
- g) patterning the second oxide layer to create a plurality of void features, wherein at least one void feature exposes a portion of the first material layer;
- h) depositing a second material layer onto the top surface of the second oxide layer and into the void features;
- and
- i) removing at least a portion of the first sacrificial material.
7 more elements
A method for fabricating an integrated circuit having an ultra low-k-region, comprising the steps of:
- a) forming a substrate having a first material layer;
- b) patterning the first material layer to form a plurality of features, each having a top surface, and to form gaps between the features;
- c) depositing a first oxide material layer onto the top surface of the features and into the gaps;
- d) depositing a first sacrificial material layer onto the first oxide layer;
- e) planarizing the first sacrificial layer;
- f) patterning the first sacrificial layer to form a plurality of void features;
- g) depositing a second oxide material layer onto patterned first sacrificial layer and into the void features;
- h) planarizing the second oxide layer;
- i) patterning the second oxide layer to form a plurality of void features wherein at least one void feature exposes a portion the first material layer;
- j) depositing a second material layer onto the second oxide layer and into the void features;
- k) polishing the second material layer to form a co-planar surface comprising the second material layer and the second oxide layer, wherein second material remains in the void features;
- and
- l) removing at least a portion of the first sacrificial material.
10 more elements
A method for fabricating an integrated circuit having an ultra low-k region, comprising the steps of:
- a) applying a first oxide layer on top of a substrate;
- b) patterning the first oxide layer and depositing a first material layer to form a plurality of first material features within the first oxide layer;
- c) removing a portion of the first oxide layer between the first material features thereby creating gaps in the first oxide layer;
- d) depositing a first sacrificial material layer onto the surface of the patterned first oxide layer and into the gaps within the first oxide layer;
- e) polishing the first sacrificial layer to form a co-planar surface comprising the first sacrificial layer and the first oxide layer, wherein first sacrificial material remains in the gaps;
- f) depositing a second oxide layer onto the co-planar surface;
- g) patterning the second oxide layer to create a plurality of void features, wherein at least one void feature exposes a portion of the first material layer;
- h) depositing a second material layer onto the top surface of the second oxide layer and into the void features, thereby creating second material features;
- i) removing a portion of the second material layer from the second oxide layer surface;
- j) removing a portion of the second oxide layer between the second material features thereby creating gaps in the second oxide layer;
- k) depositing a second sacrificial material layer onto the surface of the patterned second oxide layer and into the gaps within the second oxide layer;
- l) polishing the second sacrificial layer to form a co-planar surface comprising the second sacrificial layer and the second oxide layer, wherein second sacrificial material remains in the gaps;
- m) depositing a third oxide layer onto the co-planar surface;
- n) patterning the third oxide layer to create a plurality of void features, wherein at least one void feature exposes a portion of the second material layer;
- o) removing at least a portion of the first sacrificial material layer and the second sacrificial material layer.
12 more elements
A method for fabricating an integrated circuit having an ultra low-k region, comprising the steps of:
- a) forming a substrate having a first material layer;
- b) patterning the first material layer to form a plurality of features, each having a top surface, and to form gaps between features;
- c) depositing a first oxide material layer onto the top surface of the features and into the gaps;
- d) depositing a first ultra low-k material layer onto the first oxide layer;
- e) polishing the first ultra low-k layer to form a co-planar surface comprising the first ultra low-k layer and the first oxide material layer on the top surface of the features, wherein ultra low-k material remains in the gaps between features;
- f) depositing a second oxide material layer onto the co-planar surface
- g) patterning the second oxide material layer to create a plurality of void features, wherein at least one void feature exposes a portion of the first material layer;
- and
- h) depositing a second material layer onto the top surface of the second oxide material layer and into the void features.
6 more elements
Dependencies are inferred from the claim text.