Multiple logical bits per memory cell in a memory device
AssigneeHewlett-Packard Development Company, L.P.
InventorsKenneth K. Smith, Sarah M. Brandenberger, Darrel R. Bloomquist, Kenneth J. Eldredge, Andrew L. Van Brocklin, Peter J. Fricke
Life of this patent
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Abstract
A semiconductor substrate is provided over which electrically conductive columns are formed along with electrically conductive rows crossing over the electrically conductive columns. A plurality of memory components are formed each having a resistance value corresponding to multiple logical bits and non-volatile memory cells are each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.
Claims22
A method, comprising:
- providing a semiconductor substrate;
- forming electrically conductive columns on the semiconductor substrate;
- forming electrically conductive rows crossing over the electrically conductive columns;
- forming a plurality of memory components each having a resistance value corresponding to multiple logical bits;
- and
- forming non-volatile memory cells, each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.
A method of making a non-volatile read-only memory device, comprising:
- providing a semiconductor substrate;
- forming a first layer on the semiconductor substrate;
- forming one or more additional layers over the first layer;
- wherein forming an individual layer comprises:
- forming a plurality of conductive traces;
- and
- forming a plurality of memory components each having a resistance value corresponding to multiple logical bits where each memory component is connected between a first conductive trace and a second conductive trace.
Dependencies are inferred from the claim text.