Phase locked loop circuit for reducing electromagnetic interference and contorl method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Young Kim, Pil-Jae Jun
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Abstract
For a phase-locked loop, disclosed is a method (and corresponding apparatus) for reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the method comprising: generating a control signal having a first type, e.g., sinusoidal, of slight variation in magnitude relative to a nominal magnitude value thereof; and providing the slightly varying control signal to a voltage-controlled oscillator (“VCO”) to obtain a clock signal exhibiting a second type, e.g., sinusoidal, of slight variation in frequency relative to a nominal frequency value thereof. The slight variation is non-negligible.
Claims15
A phase locked loop (PLL) circuit for reducing electromagnetic interference (EMI) including a phase comparator for comparing the phase of an externally input reference clock signal with the phase of a feedback signal to output an up or a down signal according to the compared result, a charge pump for generating a charge signal for supplying or sinking charges in response to the up or down signal, and a loop filter for low-pass filtering the charge signal to generate direct current (DC) control voltage, the PLL circuit comprising:
- a voltage-controlled oscillator (VCO) for generating an output clock signal oscillated into an oscillating frequency corresponding to the control voltage;
- a multiphase interpolater for generating first through n-th shifted signals, which have a predetermined offset so as not to overlap one another, by using the output clock signal;
- and
- a feedback signal portion for receiving the up/down signal to determine whether the feedback signal is locked to the reference clock signal, for outputting the output clock signal as the feedback clock signal before the feedback signal is locked to the reference clock signal, and for sequentially selecting one of the first through n-th shifted clock signals to be the feedback clock signal once the feedback clock signal is locked to the reference clock signal.
A method of controlling a phase locked loop (PLL) circuit for reducing electromagnetic interference (EMI) including a phase comparator for comparing the phase of an externally input reference clock signal with the phase of a feedback signal to output an up or a down signal according to the compared result, a charge pump for generating a charge signal for supplying or sinking charges in response to the up or down signal, a loop filter for low-pass filtering the charge signal to generate direct current (DC) control voltage, and a voltage-controlled oscillator (VCO) for generating an output clock signal having an oscillating frequency corresponding to the control voltage, the method comprising:
- (a) generating first through n-th shifted clock signals, which have a predetermined offset so as not to overlap one another, by using the clock signal;
- (b) determining, according to the up/down count, whether the phase locked loop (PLL) circuit is locked;
- (c) selecting one of said shifted clock signals having the same phase as that of the clock signal and providing the selected signal to the phase comparator until it is determined that the PLL circuit is locked in the step (b);
- and
- (d) sequentially selecting one from among the first through n-th shifted clock signals to be the feedback signal once it is determined that the PLL circuit is locked in the step (b).
In a phase-locked loop, a method of reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the method comprising:
- generating a control signal having a first type of slight variation in magnitude relative to a nominal magnitude value thereof;
- and
- providing the slightly varying control signal to a voltage-controlled oscillator (“VCO”) to obtain a clock signal exhibiting a second type of slight variation in frequency relative to a nominal frequency value thereof.
In a phase-locked loop, an apparatus for reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the apparatus comprising:
- generating means for generating a control signal having a first type of slight variation in magnitude relative to a nominal magnitude relative to a nominal magnitude value thereof;
- and
- voltage-controlled oscillator (“VCO”) means for generating a clock signal exhibiting a second type of slight variation in frequency relative to a nominal frequency value thereof based upon the slightly varying control signal output by said generating means.
Dependencies are inferred from the claim text.