US 2004/0001484 A1 · Method and apparatus for implementing alterations on multiple concurrent frames

Abstract

A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes. An alteration engine receives sequentially provided aligned frame data output and alteration instructions from a selected one the plurality of frame data alteration engines and provides sequential altered frame data responsive to the received alteration instructions.

Claims18

Dependent claims

Apparatus for implementing frame header alterations on multiple concurrent frames comprising:

a plurality of frame data alteration engines, each said frame data alteration engine including a pair of a command decoder and an associated data aligner;
a command buffer arbiter sequentially receiving frame alteration commands coupled to said plurality of frame data alteration engines sequentially selecting one of said frame data alteration engines for said received frame alteration commands;
each said command decoder receiving and decoding frame alteration commands and providing frame alignment commands and alteration instructions;
and each said associated data aligner receiving frame data and coupled to said associated command decoder receiving said frame alignment commands;
each said associated data aligner selectively latching data bytes of said received frame data responsive to said frame alignment commands and sequentially providing an aligned frame data output of said predefined number of bytes;
and
an alteration engine coupled to said plurality of frame data alteration engines receiving said sequentially provided aligned frame data output and said alteration instructions from a selected frame data alteration engine and providing sequential altered frame data responsive to said received alteration instructions.

4 more elements

A method for implementing frame header alterations on multiple concurrent frames in a network processor including a plurality of distributed pico processor units (DPPUs) generating frame alteration commands coupled to a frame alteration unit, said method comprising the steps of:

providing a plurality of frame data alteration engines, each said frame data alteration engine including a pair of a command decoder and an associated data aligner;
sequentially selecting one of said frame data alteration engines for said sequentially received frame alteration commands;
utilizing each said command decoder and said associated data aligner, for receiving and decoding frame alteration commands and receiving frame data and sequentially providing alteration instructions and an aligned frame data output of said predefined number of bytes;
and
sequentially selecting one of said frame data alteration engines for applying said predetermined number of bytes of aligned frame data together with said alteration instructions to an alteration engine and providing sequential altered frame data responsive to said received alteration instructions.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus for implementing alterations on multiple concurrent frames

Life of this patent

Method and apparatus for implementing alterations on multiple concurrent frames

Life of this patent

Abstract

Claims18