Loosely-biased heterogeneous reconfigurable arrays

A heterogeneous reconfigurable array, comprising:

• a general-purpose routing network;
• and
• a plurality of clusters;
• each cluster comprising an arithmetic logic unit (“ALU”) and a multiplexer;
• the multiplexer comprising:
• a plurality of multiplexer inputs comprising:
• a multiplexer select input, and
• a first multiplexer input;
• and
• a multiplexer output;
• the ALU comprising:
• a plurality of ALU inputs, comprising:
• a first ALU data input,
• a second ALU data input, and
• an ALU instruction input;
• and
• an ALU output
• wherein the multiplexer select input is adapted to receive a multiplexer select signal generated by the ALU;
• and
• wherein the multiplexer and the ALU are connected to the general-purpose routing network;

A method of configuring an heterogeneous reconfigurable array, the heterogeneous reconfigurable array comprising a plurality of clusters, each cluster comprising a first processing element and a second processing element, the method comprising:

• receiving an application,
• selecting a first portion of the application,
• selecting a second portion of the application,
• selecting a third portion of the application,
• implementing the first portion in the plurality of first processing elements,
• implementing the second portion in the plurality of second processing elements, and
• selectively implementing the third portion in either the plurality of first processing elements, the plurality of second processing elements, or a combination thereof, based upon an availability criterion.

A heterogeneous reconfigurable array comprising:

• a plurality of arithmetic logic units (“ALU”), each comprising an ALU output and a plurality of ALU inputs;
• a plurality of multiplexers, each comprising a multiplexer control input;
• a general-purpose routing network adapted to form connections between selected ones of the plurality of ALUs and plurality of multiplexers, and
• a multiplexer control circuit connecting one of the plurality of ALU outputs to one of the plurality of multiplexer control inputs;
• wherein the multiplexer control circuit is adapted to derive a multiplexer control signal from one or more ALU output signals.

A reconfigurable array comprising:

• a first general purpose routing network comprising a first plurality of input terminals and a first plurality of output terminals;
• a second general purpose routing network comprising a second plurality of input terminals and a second plurality of output terminals;
• and
• a plurality of processing elements, each adapted to be connected to at least one terminal belonging to either the first plurality of input terminals, the first plurality of output terminals, the second plurality of input terminals, or the second plurality of output terminals;