Method and system for rate adaptation
AssigneeBroadcom Corporation
InventorDavid Wong
Life of this patent
Estimating the term…
Abstract
A media access controller, which includes an output buffer and a clock controller, is provided. The output buffer includes a first and second clock input. The first clock is configured to control data input into the buffer and the second clock is configured to control data output from the buffer. The clock controller is coupled to the output buffer and configured to regulate a first clock signal input into the first clock input to control the data input into the buffer.
Claims47
A media access controller for a network device, said controller comprising:
- an output buffer having a first clock input and a second clock input, said first clock input is for controlling data input into said buffer, and said second clock input is for controlling data output from said buffer;
- and
- a clock controller unit coupled with said output buffer at said first clock input, said clock controller unit configured to regulate a first clock signal being input to said first clock input in order to control said data input into said buffer.
A method of adapting a rate of an output signal to a rate of an output medium, said method comprising:
- providing a media access controller having an internal clock;
- inputting an external clock signal into said media access controller;
- providing a register at an output of said media access controller for outputting data to an external device, said register having a first input for control an output of the register and a second input for control an input to said register;
- providing said external clock signal to said first input of said register;
- and
- providing an internal clock signal from said internal clock to said second input of said register.
A network device comprising:
- a media access controller;
- a physical interconnect;
- an output buffer coupled with an output of said media access controller and an input of said physical interconnect, said output buffer having a first clock input and a second clock input, said first clock input is for controlling data input into said buffer from said media access controller, and said second clock input is for controlling data output from said buffer to said physical interconnect;
- and
- a clock controller unit coupled with said output buffer at said first clock input, said clock controller unit configured to regulate a first clock signal being input to said first clock input in order to control said data input into said buffer.
A media access controller for a network device, said controller comprising:
- an output buffer means for buffering output data of said media access controller, said output buffer means having a first clock input means for controlling data input into said output buffer means according to a first clock signal, and a second clock input means for controlling data output from said output buffer means according to a second clock signal;
- and
- a clock controller means for regulating said first clock signal in order to control said data input into said output buffer means.
A network device comprising:
- a media access controller means for performing layer-2 switching functions;
- a physical interconnect means for transmitting data to a physical medium according to a physical medium protocol;
- an output buffer means for buffering data being output from said media access controller means to said physical interconnect means, said output buffer means having a first clock input means for controlling data input into said output buffer means from said media access controller means, and a second clock input for controlling data output from said buffer to said physical interconnect;
- and
- a clock controller means for regulating a first clock signal being input to said first clock input means in order to control said data input into said output buffer means.
Dependencies are inferred from the claim text.