A method for testing memory cells of a memory chip having word lines, spare word lines, and bit lines, which comprises:
- providing a test logic for writing in test data to the memory cells and reading out test data from the memory cells with a first address register supplying a first address for selecting a word line;
- supplying a second address for selecting a bit line with a second address register;
- connecting a first selection decoder to the first address register;
- connecting the test logic to the first selection decoder;
- activating a word line through the first selection decoder dependent upon the first address of the first address register;
- connecting a word line to at least one control input of a plurality of switches;
- connecting a switch between each of the memory cells and each of the bit lines;
- switching at least one switch connected to a word line to conduct with an activation of the word line;
- combining two types of the bit lines to form respective bit line pairs;
- connecting a respective bit line pair to a respective amplifier circuit, a first bit line of the bit line pair being a true bit line and a second bit line of the bit line pair being a complementary bit line;
- during the reading out of a data item, comparing potentials of the true bit line and the complementary bit line of a bit line pair with the amplifier circuit, recognizing a logical one with the amplifier circuit if a potential of the true bit line is greater than a potential of the complementary bit line and recognizing a logical zero with the amplifier circuit if the potential of the true bit line is less than the potential of the complementary bit line;
- connecting the test logic to the amplifier circuits through a second selection decoder;
- selecting an amplifier circuit by connecting the second selection decoder to the second address register;
- with the test logic, writing into a memory cell connected to a complementary bit line a data item having a different physical value than a data item written into a memory cell connected to a true bit line;
- providing a repair unit with an address register for storing addresses and connecting the repair unit to the test logic;
- readdressing an access of the first selection decoder to a defective word line by the repair unit diverting the access to an address of a spare word line deposited in the address register;
- taking into consideration the address of the spare word line with the test logic in the presence of a readdressing to a spare word line, the address of the spare word line exhibiting information on whether the spare word line is a true bit line or a complementary bit line;
- only writing data corresponding to a high level into the memory cells with the test logic;
- and
- recognizing a correct operability of the memory cells by reading out the memory cells again and comparing the data read out with the data written therein.