Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface

An integrated circuit, comprising:

• a memory having multiple locations;
• a control node operable to receive a control signal having first-type edges and opposite second-type edges;
• and
• a memory-access circuit coupled to the memory and to the control node and operable to,
• access a first location of the memory in response to a first-type edge of the control signal;
• and
• access a second location of the memory in response to a second-type edge of the control signal.

An electronic system, comprising:

• an integrated circuit having,
• a memory having multiple locations,
• a control node operable to receive a control signal having first-type edges and opposite second-type edges, and
• a memory-access circuit coupled to the memory and to the control node and operable to,
• access a first location of the memory in response to a first-type edge of the control signal, and
• access a second location of the memory in response to a second-type edge of the control signal.

A method for testing a memory, comprising:

• recognizing a fall in a clock control signal and at that time in the cycle, reading a column address,
• generating a column pulse signal,
• generating a first memory address with column decoding information,
• generating a first address transition detection signal,
• generating a first read control signal,
• generating a first salatch signal,
• reading a first memory address, and
• outputting a first data on a parallel interface, and subsequently recognizing a rise in a clock control signal and at that time in the cycle,
• reading a row address,
• generating a row pulse signal,
• generating a second memory address with row decoding information based on the row address and column decoding information left unchanged,
• generating a second address transition detection signal,
• generating a second read control signal,
• generating a second salatch signal,
• reading a second memory address, and
• outputting a second data on a parallel interface.