Memory controller controlling cached DRAM
AssigneeHitachi, Ltd.
InventorSeiji Muira
Life of this patent
Estimating the term…
Abstract
According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, built-in cache memories are operated faster and at low power consumption. A memory control unit is capable of distinguishing regular memories subjected to hit checks and spare memories not subjected to hit checks. This way, if a hit check is a miss, one of the cache memories not subjected to a hit checks is subjected to a subsequent hit operation and another one of the cache memories not subjected to hit checks is not subjected to the next hit check operation.
Claims20
A semiconductor device comprising:
- a memory controller receiving commands from a CPU, and controlling a memory,
- wherein said memory, that is to be controlled, has a memory bank and a plurality of cache memories,
- wherein said plurality of cache memories are allocated against said memory bank.
A semiconductor device comprising:
- a memory controller receiving commands from a CPU, and controlling a memory,
- wherein said memory, that is to be controlled, has a memory bank and a cache memory,
- wherein said memory bank has sense amplifiers, and
- wherein a hit check is performed by said memory controller to both said cache memory and said sense amplifiers.
A semiconductor device comprising:
- a memory controller receiving commands from a CPU and controlling a memory,
- wherein said memory, that is to be controlled, has a memory bank and a cache memory, and
- wherein some portions of said cache memory are not subjected to a hit check performed by said memory controller.
A memory controlling method for an information processing system having a central processing unit, a memory control unit and a memory unit controlled by said memory control unit and being provided with a plurality of memory banks and a plurality of cache memories comprising the steps of:
- receiving a read request sent from said central processing unit at said memory control unit;
- and
- performing a hit check for both a cache memory and a sense amplifier memory in response to said read request, said sense amplifier memory located in said plurality of memory banks.
Dependencies are inferred from the claim text.