Low-cost, serially-connected, multi-level mask-programmable read-only memory
AssigneeMatrix Semiconductor, Inc.
InventorMark G. Johnson
Life of this patent
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Abstract
An integrated circuit includes a serially-connected, multi-level, mask-programmed read-only memory array. The memory cells are preferably programmed using selective ion implantation of at least two threshold-adjusting ion implants during the manufacture of the integrated circuit to store more than one bit of information within each memory cell, which are chosen to generate an evenly spaced set of different transistor threshold voltages.
Claims27
An integrated circuit comprising an array of serially-connected, multi-level, mask-programmable read-only memory cells.
An integrated circuit including a memory array comprising:
- a plurality of memory cell squads, each squad comprising a corresponding plurality of serially-connected memory cells, each squad coupled at one end thereof to an associated bit line of the memory array;
- each of said memory cells comprising a read-only memory cell which is mask-programmable to store more than one bit of information therein.
An integrated circuit memory array comprising:
- a plurality of memory cell squads, each squad comprising a corresponding plurality of serially-connected single transistor memory cells, each squad coupled at one end thereof to an associated bit line of the memory array;
- each of said memory cells comprising a read-only memory cell which is programmed during semiconductor manufacture by selectively ion implanting a combination of N different ion implantations to store more than one bit of information therein.
A method of fabricating an integrated circuit memory array comprising the steps of:
- forming a plurality of memory cell squads, each squad comprising a corresponding plurality of serially-connected single transistor memory cells, each squad coupled at one end thereof to an associated bit line of the memory array;
- using at least two different masks, selectively ion implanting a combination of at least two possible ion implantations into each memory cell to encode more than one bit of information per memory cell, and thereby resulting in a read-only memory cell.
A computer readable medium encoding an integrated circuit including a memory array, said encoded memory array comprising:
- a plurality of memory cell squads, each squad comprising a corresponding plurality of serially-connected memory cells, each squad coupled at one end thereof to an associated bit line of the memory array;
- each of said memory cells comprising a read-only memory cell which is mask-programmable to store more than one bit of information therein.
Dependencies are inferred from the claim text.