Integrated circuit, system development method, and data processing method
AssigneeFujitsu Limited
InventorsMiyoshi Saito, Yoshio Hirose
Life of this patent
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Abstract
An integrated circuit includes a processor. An arithmetic logic circuit group includes a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner. Parameter-based dedicated hardware can change a process specification thereof by parameter setting. An intermodule interface connects the processor, the arithmetic logic circuit group, and the parameter-based hardware to each other.
Claims13
An integrated circuit, comprising:
- a processor;
- an arithmetic logic circuit group including a plurality of operation units and a connection channel connecting said operation units in a reconfigurable manner;
- parameter-based dedicated hardware capable of changing a process specification thereof by parameter setting;
- and
- an intermodule interface connecting said processor, said arithmetic logic circuit group, and said parameter-based hardware to each other.
A system development method of programming an integrated circuit that includes a processor, an arithmetic logic circuit group having a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner, parameter-based dedicated hardware capable of changing a process specification thereof by parameter setting, and an intermodule interface connecting the processor, the arithmetic logic circuit group, and the parameter-based dedicated hardware to each other, said system development method comprising the steps of:
- generating objects and relationships among the objects through object analysis;
- generating processes each including at least one of the objects by putting the objects that are related to each other together;
- and
- assigning the processes to the processor, the arithmetic logic circuit group, and the parameter-based dedicated hardware of the integrated circuit.
A data processing method, comprising the step of:
- executing a multi process operation in an integrated circuit including a processor, an arithmetic logic circuit group having a plurality of operation units and a connection channel connecting said operation units in a reconfigurable manner, parameter-based dedicated hardware capable of changing a process specification thereof by parameter setting, and an intermodule interface connecting said processor, said arithmetic logic circuit group, and said parameter-based dedicated hardware to each other, by assigning a plurality of processes of data processing to said processor, said arithmetic logic circuit group, and said parameter-based dedicated hardware.
A data processing method, comprising the step of:
- executing a multi process operation in an integrated circuit including a processor, an arithmetic logic circuit group having a plurality of operation units and a connection channel connecting said operation units in a reconfigurable manner, parameter-based dedicated hardware capable of changing a process specification thereof by parameter setting, a reconfigurable gate array allowing logic change at a gate level, and an intermodule interface connecting said processor, said arithmetic logic circuit group, said reconfigurable gate array, and said parameter-based dedicated hardware to each other, by assigning a plurality of processes of data processing to said processor, said arithmetic logic circuit group, said reconfigurable gate array, and said parameter-based dedicated hardware.
A data processing method, comprising the step of:
- executing a multi process operation in an integrated circuit including a processor, an arithmetic logic circuit group having a plurality of operation units and a connection channel connecting said operation units in a reconfigurable manner, parameter-based dedicated hardware capable of changing a process specification thereof by parameter setting, dedicated hardware executing a specific process, and an intermodule interface connecting said processor, said arithmetic logic circuit group, said parameter-based dedicated hardware, and said dedicated hardware executing the specific process to each other, by assigning a plurality of processes of data processing to said processor, said arithmetic logic circuit group, said parameter-based dedicated hardware, and said dedicated hardware executing the specific process.
Dependencies are inferred from the claim text.