Switching point detection circuit and semiconductor device using the same

A switching point detection circuit for detecting a switching point according to a fabrication condition of MOS transistor, the circuit comprising:

• a reference voltage generation unit for generating a first reference voltage, which is higher than a half power supply voltage, and a second reference voltage, which is lower than a half power supply voltage;
• a first CMOS inverter receiving the first reference voltage, having a switching point at the half power supply voltage;
• and
• a second CMOS inverter receiving the second reference voltage and having a switching point at the half power supply voltage.

A semiconductor device comprising:

• a buffering means for buffering an input signal;
• a switching point detection means for detecting switching point variation of a CMOS inverter according to a fabrication condition of a MOS transistor;
• and
• a delay means for delaying the input signal under control of the switching point detection means.

A semiconductor device comprising:

• a switching point detection means for detecting switching point variation of a CMOS inverter according to a fabrication condition of a MOS transistor, comprising
• a reference voltage generation unit for generating a reference voltage;
• a first CMOS inverter, in which an NMOS transistor is dominant for the reference voltage, receiving the reference voltage;
• and
• a second CMOS inverter, in which a PMOS transistor is dominant for the reference voltage, receiving the reference voltage;
• a first multiplexer for selectively outputting a power supply voltage or an input signal according to an output signal of the first CMOS inverter;
• a second multiplexer for selectively outputting a power supply voltage or an input signal according to an output signal of the second CMOS inverter;
• a third CMOS inverter for inverting the input signal;
• a first pull-up means for performing a pull-up operation for an output of the third CMOS inverter according to an output signal of the first multiplexer;
• and
• a second pull-up means for performing a pull-up operation for an output of the third CMOS inverter according to an output signal of the second multiplexer.

A semiconductor memory device, comprising:

• a switching point detection means for detecting switching point variation of a CMOS inverter according to a fabrication condition of a MOS transistor, includes:
• a reference voltage generation unit for generating a first reference voltage, which is higher than a half power supply voltage, and a second reference voltage, which is lower than a half power supply voltage;
• a first CMOS inverter receiving the first reference voltage, having a switching point at the half power supply voltage;
• and
• a second CMOS inverter receiving the second reference voltage and having a switching point at the half power supply voltage;
• a first multiplexer for selectively outputting a power supply voltage or an input signal according to an output signal of the first CMOS inverter;
• a second multiplexer for selectively outputting a power supply voltage or an input signal according to an output signal of the second CMOS inverter;
• a third CMOS inverter for inverting the input signal;
• a first pull-up means for performing a pull-up operation for an output of the third CMOS inverter according to an output signal of the first multiplexer;
• and
• a second pull-up means for performing a pull-up operation for an output of the third CMOS inverter according to an output signal of the second multiplexer.