DLL with false lock protector
AssigneeBerkana Wireless, Inc.
InventorsSang Jin Byun, Beomsup Kim, Chan-Hong Park
Life of this patent
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Abstract
A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.
Claims11
A delay locked loop for false lock protection comprising:
- a reference clock sending a first signal;
- a delay line for delaying the first signal and sending a second signal to an output clock;
- a phase detector for detecting a phase in the first signal and the second signal;
- a comparator for comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data;
- a determinator, using the output data from the comparator, for determining a range to be associated with the rising edge of the second signal, with regard to the reference clock;
- and
- a controller for controlling the delay line using the phase detector and the output data from the comparator and the range determined by the determinator.
A method for a delay locked loop for false lock protection comprising:
- sending a first signal from a reference clock;
- delaying the first signal using a delay line and sending a second signal to an output clock;
- detecting a phase, using a phase detector, in the first signal and the second signal;
- comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data;
- determining a range to be associated with the rising edge of the second signal, with regard to the reference clock;
- and
- controlling the delay line using the phase detector and the output data from the comparator and the range.
Dependencies are inferred from the claim text.