Digital clock rate multiplier method and apparatus
AssigneeAgere Systems Inc.
InventorTony S. El-Kik
Life of this patent
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Abstract
A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.
Claims21
A method for multiplying an input signal comprising the steps of:
- digitally generating a first delay signal and a second delay signal based on the input signal;
- generating a first clock signal based on said first delay signal;
- generating a second clock signal based on said second delay signal;
- and
- combining said first and second clock signals to produce a multiplied output signal.
A digital multiplier for multiplying an input signal comprising:
- a digital delay signal generator for generating a first delay signal and a second delay signal based on the input signal;
- and
- a clock circuit coupled to said digital delay signal generator for producing a multiplied output signal based at least partially on said first and second delay signals.
A digital delay circuit for delaying an input signal comprising:
- one or more delay elements connected in series, a first of said delay elements receiving the input signal;
- a first multiplexer coupled to said one or more delay elements having a plurality of input to receive the input signal as delayed by each of said delay elements, said first multiplexer further having a control terminal and an output terminal;
- a second multiplexer coupled to at least a portion of said one or more delay elements having a plurality of inputs to receive at least a portion of the input signals as delayed by each of said delay elements, said second multiplexer further having a control terminal and an output terminal;
- a counter having a clock terminal coupled to the output of said first multiplexer and a count terminal coupled to the control terminal of said first multiplexer, said counter enabled during a first period of the input signal, said counter, when enabled, counting rising edges received from said first multiplexer, each time said counter counts a rising edge, said counter increments a count signal at said count terminal, thereby shifting said first multiplexer to pass the next delayed version of the input signal;
- and
- a divider coupled between the count terminal of said counter and the control terminal of said second multiplexer for dividing said count signal, thereby configuring said second multiplexer to pass said input signal delayed by a second period of the input signal to produce a delayed clock signal.
A method for delaying an input signal comprising the steps of:
- producing a plurality of delayed versions of the input signal;
- enabling a counter for a period of the input signal;
- counting specified edges of said plurality of delayed version when said counter is enabled;
- and
- selecting a delayed output signal from said plurality of delayed versions based on the number of specified edges counted.
A method for resetting a first signal generator that is set by rising edges of an input signal and a second signal generator that is set by falling edges of the input signal, the outputs of said first and second signal generators being combined to produce a multiplied output signal, said method comprising the steps of:
- digitally generating a first delayed clock signal based on the input clock for resetting the first signal generator;
- and
- digitally generating a second delayed clock signal based on the input clock for resetting the second signal generator.
Dependencies are inferred from the claim text.