Clock divider and method for dividing clock signal in DLL circuit
AssigneeHynix Semiconductor Inc.
InventorYoung-Jin Jeon
Life of this patent
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Abstract
A clock divider of a DLL circuit for generating an internal clock signal synchronized to an external clock signal is disclosed which includes a first clock divider for generating a first clock signal dividing a clock signal having the same period with the external clock signal, a second clock divider for generating a second clock signal and a third clock signal by dividing the first clock signal, a selection signal generator for generating a selection signal in response to a plurality control signals and a clock signal selector for selectively outputting the second clock signal or third clock signal in response to the selection signal.
Claims12
A clock divider in a DLL circuit for generating an internal clock signal synchronized to an external clock signal, the clock divider comprising:
- a first clock dividing means for generating a first clock signal dividing a clock signal having the same period with the external clock signal;
- a second clock dividing means for generating a second clock signal and a third clock signal by dividing the first clock signal outputted from the first clock dividing means;
- a selection signal generation means for generating a selection signal in response to a plurality control signals;
- and
- a clock signal selection means for selectively outputting the second clock signal or third clock signal in response to the selection signal.
A method for dividing a clock signal in a DLL circuit for generating an internal clock signal synchronized to an external clock signal, the method comprising:
- generating a first clock signal by dividing a clock signal having the same period with the external clock signal;
- generating a second clock signal and a third clock signal by dividing the first clock signal;
- generating a selection signal by receiving a long locking signal generated when a high frequency clock signal is inputted to the DLL circuit, a DLL enable signal generated when the DLL is enabled and a dividing clock signal selection. enable signal to be a logic high state only for initial four cycles after the DLL circuit is turned on;
- and
- selectively outputting the second clock signal for a high frequency clock signal or the third clock signal for a low frequency clock signal in response to the selection signal.
Dependencies are inferred from the claim text.