Decoding circuit for wafer burn-in test
AssigneeHynix Semiconductor Inc.
InventorJi Eun Jang
Life of this patent
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Abstract
A decoding circuit for a wafer burn-in test internally generates a strobe signal during the wafer burn-in test by using external input address signals, thereby decreasing the number of input pads required to receive external input strobe address signals. A plurality of pulse generating units respectively delay and logically combine a plurality of external input address signals to generate pulses. Thereafter, an internal strobe signal is generated by respectively delaying and logically operating the pulses from the pulse generating units.
Claims19
A decoding circuit for a wafer burn-in test, comprising:
- an address control unit for buffering a plurality of externally inputted address signals and generating a plurality of internal address signals in order to selectively enable word line driving signals during the wafer burn-in test;
- a strobe signal generating unit for generating a plurality of delay pulse signals having a predetermined pulse width according to the plurality of address signals, and generating a strobe signal by logically operating the plurality of delay pulse signals wherein each delay pulse signal is enabled when its corresponding address signal inputted externally is transited, and the strobe signal has a pulse when at least one delay pulse signal is enabled;
- and
- a decoding unit for decoding the plurality of internal address signals according to the strobe signal from the strobe signal generating unit, and selectively outputting the word line driving signals.
A decoding circuit for a wafer burn-in test, comprising:
- an address control means for buffering a plurality of externally inputted address signals, and generating a plurality of internal address signals in order to selectively enable word line driving signals during the wafer burn-in test;
- a strobe signal generating means for generating a strobe signal according to a transition state of the plurality of externally inputted address signals;
- and
- a decoding means for decoding the plurality of internal address signals according to the strobe signal from the strobe signal generating means, and selectively outputting the word line driving signals, wherein the strobe signal generating means comprises:
- a plurality of first pulse generating means for respectively delaying a plurality of pulse signals having a predetermined pulse width according to the plurality of externally inputted address signals, and outputting a plurality of delay pulse signals;
- and a second pulse generating means for generating the strobe signal having a pulse of a predetermined width when at least one delay pulse signals is transited among the plurality of delay pulse signals.
Dependencies are inferred from the claim text.