Fault-tolerant inverter circuit

A fault-tolerant inverter circuit, comprising:

• a first P-type transistor and a first N-type transistor are constructed a first inverter, wherein the gate of said first P-type transistor and the gate of said first N-type transistor are coupled to form an inputting end of said first inverter for receiving an input signal, and the drain of said first P-type transistor and the drain of said first N-type transistor are coupled to form an outputting end of said first inverter;
• a second P-type transistor and a second N-type transistor are constructed a second inverter, wherein the gate of said second P-type transistor and the gate of said second N-type transistor are coupled to form an inputting end of said second inverter and connect to the outputting end of said first inverter, and the drain of said second P-type transistor and the drain of said second N-type transistor are coupled to form an outputting end of said second inverter;
• and
• a third P-type transistor and a third N-type transistor are constructed a third inverter, wherein the gate of said third P-type transistor and the gate of said third N-type transistor are coupled to form an inputting end of said third inverter and connect to the outputting end of said second inverter, and the drain of said third P-type transistor and the drain of said third N-type transistor are coupled to form an outputting end of said third inverter for outputting a output signal,
• herein, the inputting end of said first inverter is linked to the inputting end of said third inverter, and the outputting end of said first inverter is linked to the outputting end of said third inverter.

A fault-tolerant inverter circuit, comprising:

• a first inverter element, the inputting end of said first inverter element is received an input signal, wherein a gate signal leading wiring is used to lead out a gate signal from a gate wiring, and a source/drain signal wiring is used to lead out a drain signal, said gate signal leading wiring and said source/drain signal wiring of said first inverter element are located on different circuit layers;
• a second inverter element, the inputting end of said second inverter element is connected to the outputting end of said first inverter element, wherein a gate signal leading wiring is used to lead out a gate signal from a gate wiring, and a source/drain signal wiring is used to lead out a drain signal, said gate signal leading wiring and said source/drain signal wiring of said second inverter element are located on different circuit layers;
• and
• a third inverter element, the inputting end of said third inverter element is connected to the outputting end of said second inverter element, the outputting end of said third for outputting a output signal, wherein a gate signal leading wiring is used to lead out a gate signal from a gate wiring, and a source/drain signal wiring is used to lead out a drain signal, said gate signal leading wiring and said source/drain signal wiring of said third inverter element are located on different circuit layers,
• herein, the inputting end of said first inverter is linked to the inputting end of said third inverter, and the outputting end of said first inverter is linked to the outputting end of said third inverter.