Device and method with generic logic blocks

A programmable logic device including a plurality of logic blocks and routing resources for transmitting signals between the blocks, a logic block comprising:

• a plurality of product term circuits operable in logic mode to generate product terms from multiple input signals and operable in memory mode to store data bits, each product term circuit including a configuration cell operable to store a configuration bit in logic mode and a data bit in memory mode;
• a first mode select circuit operable to select input signals for a first group of the product term circuits in logic mode and to select a first memory address signal for the first group of product term circuits in memory mode;
• and
• a second mode select circuit operable to select input signals for a second group of the product term circuits in logic mode and to select a second memory address signal for the second group of product term circuits in memory mode.

A programmable logic device including a plurality of logic blocks and routing resources for transmitting signals between the blocks, a logic block comprising:

• a plurality of product term circuits operable in logic mode to generate product terms from multiple input signals and operable in memory mode to act as a first-in-first-out (FIFO) memory that stores and retrieves data bits in a FIFO order, each product term circuit including a configuration cell operable to store a configuration bit in logic mode and a data bit in memory mode;
• a mode select circuit operable in logic mode to select input signals for the product term circuits and in memory mode to select a read address signal for the product term circuits;
• a read counter operable to provide the read address signal to the mode select circuit;
• a write counter operable to provide a write address signal to the product term circuits;
• and
• FIFO flag logic operable to compare the value of the read address signal to the value of the write address signal and generate one or more flags in response to the comparison.

A programmable logic device including a plurality of logic blocks and routing resources for transmitting signals between the blocks, a logic block comprising:

• a plurality of product term circuits operable in logic mode to generate product terms from multiple input signals and operable in memory mode to act as a content addressable memory (CAM) that compares data bits in each product term circuit against an input word, each product term circuit including a configuration cell operable in logic mode to store a configuration bit and in memory mode to store a data bit;
• a mode select circuit operable in logic mode to select a source of input signals for the configuration cells and in memory mode to select a source of input words for the configuration cells;
• and
• an address encoder operable to obtain results of the input word-data bits comparison performed by the product term circuits and to encode the results into an address.