Converting bits to vectors in a programmable logic device

An interface within a PLD, comprising:

• an input port coupled to unordered bits in a PLD domain;
• a first stage coupled to the input port, the first stage including a first array of programmable fuses and a first set of multiple parallel signal conductors, the fuses allowing programmable connection between selected unordered bits from the input port and selected ones of the multiple parallel signal conductors from the first set;
• and
• a second stage coupled to the first stage and having a second array of programmable fuses and a second set of multiple parallel signal conductors, the second array of programmable fuses allowing programmable connection between selected ones of the first set of multiple parallel signal conductors and the second set of multiple parallel signal conductors to receive the unordered bits from the first set of multiple parallel conductors and convert the bits into fixed-width vectors to use in the vector processing block.

A method of converting unordered bits in a PLD domain to fixed-width vectors for use in a vector domain, comprising:

• receiving the unordered bits from the PLD domain;
• selecting which of the unordered bits to use in the vector domain;
• and
• converting the unordered bits into fixed-width vectors to use in the Vector domain.

A circuit for converting unordered bits in a PLD domain to fixed-width vectors for use in a vector domain, comprising:

• means for receiving the unordered bits from the PLD domain;
• means for selecting which of the unordered bits to use in the vector domain;
• and
• means for converting the unordered bits into fixed-width vectors.

A field programmable gate array (FPGA), comprising:

• an FPGA domain including multiple programmable logic blocks that process data in the form of individual bits;
• a vector domain including one or more engines that process data in the form of vectors that each include multiple bits;
• and
• an interface coupled between the FPGA domain and the vector domain, the interface operable to convert individual bits received from the FPGA domain into a vector for processing in the vector domain.