Stacked multi-chip package, process for fabrication of chip structuring package, and process for wire-bonding

A stacked multi-chip package comprising:

• a substrate;
• a first chip including an upper face which includes a first electrode pad, a lower face whose area is smaller than an area of the upper face, and a side face connecting the upper face and the lower face, the lower face being fixed on the substrate;
• first metallic wire electrically connecting the first electrode pad with the substrate;
• a second chip disposed below the first chip and including an upper face which includes a second electrode pad, the second chip being disposed at a location separated by a predetermined distance from the side face of the first chip;
• and
• second metallic wire electrically connecting the second electrode pad with the substrate.

A stacked multi-chip package comprising:

• a substrate including a front face;
• a chip body fixed at the front face of the substrate and including a first face, with a gap being formed between the first face and the front face of the substrate and a connecting portion which connects the chip body with the substrate;
• and
• a fixed chip fixed at the front face of the substrate with out contacting the chip body, at least a portion of the fixed chip being disposed in the gap,
• wherein the portion of the fixed chip that is disposed in the gap includes an upper face which opposes the first face of the chip body, and the upper face is disposed upward relative to the connecting portion.