Semiconductor structure
AssigneeIntel Corporation
InventorJames Powers
Life of this patent
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AssigneeIntel Corporation
InventorJames Powers
Estimating the term…
The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.
A method comprising:
A method comprising:
A structure comprising:
Dependencies are inferred from the claim text.