Non-volatile memory cells utilizing substrate trenches

An array of non-volatile memory cells on a semiconductor substrate, comprising:

• elongated source and drain diffusions having their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,
• an array of floating gates arranged in columns extending in the first direction and rows extending in the second direction, individual memory cells having one edge of their floating gates positioned over one of the diffusions,
• trenches in the substrate adjacent opposite edges of the floating gates in the second direction, said trenches containing another one of the diffusions,
• elongated control gates having lengths extending in the second direction along rows of floating gates and being capacitively coupled with the sidewalls of the trenches that are positioned immediately adjacent the floating gates, and
• elongated erase gates having lengths extending in the second direction across the array along and capacitively coupled with rows of floating gate edges.

An array of non-volatile memory cells on a semiconductor substrate, comprising:

• elongated source and drain diffusions having their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,
• an array of floating gates arranged in columns extending in the first direction and rows extending in the second direction, individual memory cells having one edge of their floating gates positioned over one of the diffusions,
• trenches in the substrate adjacent opposite edges of the floating gates in the second direction, said trenches containing another one of the diffusions,
• elongated word lines having lengths extending in the second direction over rows of floating gates and having select gates capacitively coupled with the sidewalls of the trenches that are positioned immediately adjacent the floating gates, and
• elongated steering gates having lengths extending in the first direction across the array over and capacitively coupled with columns of floating gates.

An array of non-volatile memory cells on a semiconductor substrate, comprising:

• elongated trenches formed in the substrate with their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,
• elongated source and drain diffusions with their lengths extending in the first direction and being spaced apart in the second direction such that first alternate diffusions are formed in the substrate along a bottom of individual trenches and that second alternate diffusions are formed in the substrate along a top surface thereof,
• an array of floating gates spaced apart across the top surface of the substrate in the first direction and individually spanning between a trench and substrate surface diffusion in the second direction without extending downward into a trench,
• elongated word lines having lengths extending in the second direction over floating gates and being spaced apart in the first direction, said word lines having select gates extending downward into the trenches to capacitively couple with opposing sidewalls of the trenches, and
• elongated third gates extending across the array and individually being capacitive coupled with a plurality of floating gates.

An array of non-volatile memory cells on a semiconductor substrate, comprising:

• elongated trenches formed in the substrate with their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,
• elongated source and drain diffusions with their lengths extending in the first direction being formed in the substrate along a bottom and extending upward along one sidewall of the individual trenches to a top surface of the substrate but being absent from an opposite sidewall of the individual trenches, said one sidewall of the trenches facing the same direction,
• an array of floating gates spaced apart across the top surface of the substrate in the first direction and spanning between the trenches in the second direction without extending downward into the trenches, and
• elongated word lines having lengths extending in the second direction over floating gates and being spaced apart in the first direction, said word lines having select gates extending downward into the trenches to capacitively couple with said opposite trench sidewalls.

A process of fabricating a non-volatile memory cell array, comprising:

• forming strips of polysilicon across a semiconductor substrate with a layer of dielectric therebetween, the polysilicon strips being elongated in a first direction across the substrate and being spaced apart in a second direction, wherein the first and second directions are orthogonal with each other,
• etching trenches into the substrate between at least every other one of the polysilicon strips, said trenches being defined by positions of the polysilicon strips and having lengths extending in the first direction,
• thereafter implanting ions along the lengths of the trenches to form elongated sources and drains in said trenches,
• thereafter separating the strips of polysilicon into individual floating gates, thereby forming a two-dimensional array of floating gates,
• forming a first plurality of elongated gates extending across the array of floating gates in the first direction that extend into the trenches crossed by them, and
• forming a second plurality of elongated gates.

A process of fabricating a non-volatile memory cell array, comprising:

• forming strips of polysilicon across a semiconductor substrate with a layer of dielectric therebetween, the polysilicon strips being elongated in a first direction across the substrate and being spaced apart in a second direction, wherein the first and second directions are orthogonal with each other,
• etching trenches into the substrate in each space between the polysilicon strips, a width of said trenches in the second direction being defined by positions of the polysilicon strips and having lengths extending in the first direction,
• thereafter implanting ions along the lengths of the trenches in their bottoms and only one of opposing sidewalls to form elongated sources and drains in said trenches,
• thereafter separating the strips of polysilicon into individual floating gates, thereby forming a two-dimensional array of floating gates, and
• forming a plurality of elongated gates extending across the array of floating gates in the first direction that extend into the trenches crossed by them.

An array of non-volatile memory cells that individually include at least one storage element transistor and at least one select transistor in series between source and drain regions of a substrate, comprising:

• a recess in a surface of the substrate,
• said at least one storage element of the individual cells being positioned on the surface of the substrate with a first dielectric therebetween and adjacent one edge of the recess,
• a gate extending into the recess with a second dielectric therebetween in order to form a channel of the select transistor along opposing walls and a bottom surface of the recess, and
• components of the source and drain diffusions, recesses and storage elements being formed in a regular non-mirrored pattern in a direction across the array through these components.

An array of non-volatile memory cells, the memory cells individually comprising:

• source and drain regions formed in a planar surface of a substrate a distance apart from each other, thereby defining a semi-conductive channel of the memory cell therebetween,
• first and second memory storage elements positioned over the planar substrate surface adjacent the respective source and drain regions,
• a recess formed in the substrate surface between the first and second storage elements in a manner to have sidewalls and a bottom, and
• a select transistor gate extending into the recess in a manner to have field coupling with the recess sidewalls and bottom through a dielectric layer therebetween, thereby utilizing the recess sidewalls as part of the memory cell channel.