US 2004/0000686 A1 · INTEGRATED DRAM PROCESS/STRUCTURE USING CONTACT PILLARS

Abstract

A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Claims53

Dependent claims

An embedded DRAM memory cell, comprising:

an access transistor, the access transistor comprising:
a source and a drain within a substrate, and having a channel region therebetween;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
the access transistor covered by a first insulating layer;
a bit line contact pillar extending through the first insulating layer and contacting the drain of the access transistor, the bit line contact pillar composed of a contact conductive material;
a three dimensional capacitor structure comprising:
a storage plate comprising a storage contact pillar residing within a trench formed in the first insulating layer, and coupled to the source of the access transistor, and laterally spaced away from a side wall of the trench;
and
a capacitor dielectric layer overlaying the trench and the storage contact pillar within the trench;
and
a ground plate overlying the capacitor dielectric layer;
a second insulating layer overlying the access transistor, and having a first opening overlying the bit line contact pillar and a second opening overlying the trench;
and
a conductive material within the first and second openings, respectively, wherein the conductive material within the first opening comprises a bit line contact and the conductive material within the second opening comprises the ground plate of the three dimensional capacitor structure.

12 more elements

An embedded DRAM memory cell, comprising:

an access transistor, the access transistor comprising:
a source and a drain within a substrate, and having a channel region therebetween;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
the access transistor covered by a first insulating layer;
a bit line contact pillar extending through the first insulating layer and contacting the drain of the access transistor, the bit line contact pillar composed of a contact conductive material;
a three dimensional capacitor structure comprising:
a storage plate comprising a storage contact pillar residing within a trench formed in the first insulating layer, and coupled to the source of the access transistor, and laterally spaced away from a side wall of the trench;
and
a capacitor dielectric layer overlaying the trench and the storage contact pillar within the trench and defining a ground plate region surrounding the storage contact pillar;
a conductive plate material residing in the ground plate region surrounding the storage contact pillar with the capacitor dielectric layer disposed therebetween, the conductive plate material forming a ground plate for the three dimensional capacitor structure;
a second insulating layer overlying the access transistor and the three dimensional capacitor structure, the second insulating layer having a first opening overlying the bit line contact pillar and a second opening overlying a portion of the ground plate;
and
a conductive material within the first and second openings, respectively, wherein the conductive material within the first opening comprises a bit line contact and the conductive material within the second opening comprises a ground plate contact for the ground plate of the three dimensional capacitor structure.

11 more elements

An embedded DRAM memory cell, comprising:

an access transistor, the access transistor comprising:
a source and a drain within a substrate, and having a channel region therebetween;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
the access transistor covered by a first insulating layer;
a bit line contact pillar extending through the first insulating layer and contacting the drain of the access transistor, the bit line contact pillar composed of a contact conductive material;
a storage contact pillar extending through the first insulating layer and contacting the source of the access transistor;
a three dimensional capacitor structure comprising:
an active region formed in the substrate and electrically isolated from the source and drain of the access transistor, the active region comprising a ground plate region of the capacitor structure;
a ground plate contact pillar residing within a trench formed in the first insulating layer, the ground plate contact pillar composed of the contact conductive material, and laterally spaced away from a side wall of the trench;
and
a capacitor dielectric layer overlaying the trench and the ground plate contact pillar within the trench and defining a storage plate region between the sidewall of the trench and the ground plate contact pillar;
a conductive plate material residing in the storage plate region, the conductive plate material forming a storage plate of the capacitor structure;
a second insulating layer overlying the access transistor and the three dimensional capacitor structure, the second insulating layer having a first opening overlying the bit line contact pillar and a second opening overlying both the storage contact pillar and the storage plate;
and
a conductive material within the first and second openings, wherein the conductive material within the first opening comprises a bit line contact and the conductive material within the second opening comprises an electrical connection between the source of the access transistor and the storage plate of the capacitor structure.

13 more elements

A method of forming a capacitor under bitline DRAM memory cell, comprising:

forming within a first insulating layer an access transistor for the memory cell comprising:
a source and a drain within a substrate, and having a channel region therebetween, the source, drain and the channel region each defining an active area of the substrate;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
forming within the first insulating layer a bit line contact pillar of a contact conductive material extending through the first insulating layer and contacting the drain of the access transistor for electrical connection with a bit line;
forming within the first insulating a storage contact pillar of the contact conductive material extending through the first insulating layer and contacting the source of the access transistor for electrical connection with a memory cell capacitor;
forming a trench in the first insulating layer extending down toward the substrate, exposing a portion of the storage contact pillar operable as a storage plate of the memory cell capacitor;
depositing a capacitor dielectric layer over the trench, thereby covering the exposed portion of the storage contact pillar;
depositing a second insulating layer over the capacitor dielectric layer;
removing portions of the second insulating layer to expose an opening in the second insulating layer overlying the bit line contact pillar and to define a capacitor plate area associated with the trench;
removing portions of the capacitor dielectric layer to expose an opening in the capacitor dielectric layer overlying the bit line contact pillar for a contact to the bit line contact pillar;
and
depositing and planarizing a conductive material layer over the capacitor dielectric layer in the trench capacitor plate area, and the bit line contact pillar, wherein the conductive material layer in the trench capacitor plate area is operable as a ground plate of the memory cell capacitor.

10 more elements

A method of forming a capacitor under bitline DRAM memory cell, comprising:

forming within a first insulating layer an access transistor for the memory cell comprising:
a source and a drain within a substrate, and having a channel region therebetween, the source, drain and the channel region each defining an active area of the substrate;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
forming within the first insulating layer a bit line contact pillar of a contact conductive material extending through the first insulating layer and contacting the drain of the access transistor for electrical connection with a bit line;
forming within the first insulating layer a storage contact pillar of the contact conductive material extending through the first insulating layer and contacting the source of the access transistor for electrical connection with a memory cell capacitor;
forming a trench in the first insulating layer extending down toward the substrate, exposing a portion of the storage contact pillar operable as a storage plate of the memory cell capacitor;
depositing a capacitor dielectric layer over the trench, thereby covering the exposed portion of the storage contact pillar;
depositing and planarizing a layer of conductive capacitor plate material over the capacitor dielectric layer in the trench defining a ground plate of the memory cell capacitor;
depositing and planarizing a second insulating layer over the capacitor dielectric layer;
removing portions of the second insulating layer to expose an opening in the second insulating layer overlying the bit line contact pillar and an opening overlying a portion of the capacitor plate material used as the ground plate;
and
depositing and planarizing a conductive material layer through the openings in the second insulating layer for contact to the bit line contact pillar and a portion of the capacitor plate material operable as the ground plate of the memory cell capacitor.

10 more elements

A method of forming a capacitor under bitline DRAM memory cell, comprising:

forming within a first insulating layer an access transistor for the memory cell comprising:
a source and a drain within a substrate, and having a channel region therebetween, the source, drain and the channel region each defining an active area of the substrate;
and
a gate dielectric and a gate electrode overlying the channel region, the gate electrode forming a portion of a word line associated with the DRAM memory cell;
forming within the first insulating layer a bit line contact pillar of a contact conductive material extending through the first insulating layer and contacting the drain of the access transistor for electrical connection with a bit line;
forming within the first insulating layer a storage contact pillar of the contact conductive material extending through the first insulating layer and contacting a ground plane region of a memory cell capacitor;
forming within the first insulating layer a ground plate contact pillar composed of the contact conductive material extending through the first insulating layer and contacting a ground plane region of the memory cell capacitor;
forming a trench in the first insulating layer extending down toward the substrate, exposing a portion of the ground plate contact pillar operable as a ground plate of the memory cell capacitor, wherein the ground plate contact pillar resides within the trench formed in the first insulating layer;
depositing a capacitor dielectric layer over the trench, thereby covering the exposed portion of the ground plate contact pillar;
depositing and planarizing a layer of conductive capacitor plate material over the capacitor dielectric layer in the trench, thereby defining a storage plate of the memory cell capacitor;
depositing and planarizing a second insulating layer;
removing portions of the second insulating layer to expose a first opening in the second insulating layer overlying the bit line contact pillar and a second opening overlying the storage contact pillar and a portion of the capacitor plate material used as the storage plate;
and
depositing and planarizing a conductive material layer through the openings in the second insulating layer for contact to the bit line contact pillar, the storage contact pillar and a portion of the storage plate, wherein the conductive material within the second opening comprises an electrical connection between the source of the access transistor and the storage plate of the capacitor structure.

11 more elements

Dependencies are inferred from the claim text.

Integrated dram process/structure using contact pillars

Life of this patent

Integrated dram process/structure using contact pillars

Life of this patent

Abstract

Claims53