Semiconductor memory devices and methods for manufacturing the same using sidewall spacers

A semiconductor memory device comprising:

• a semiconductor substrate including a plurality of active regions, a plurality of word line structures passing over the active regions, source and drain regions on the active regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions;
• an interlevel insulating layer on the semiconductor substrate;
• etch stoppers on the interlevel insulating layer;
• storage node contact plugs in the interlevel insulating layer and the etch stoppers;
• storage node electrodes, which comprise a plurality of conductive line patterns separated in predetermined intervals while having a predetermined height, contacting the storage node contact plugs;
• and
• supporters between the storage node electrodes and extending perpendicular to an extending direction of the line patterns of the storage node electrodes;
• wherein, the plurality of line patterns comprise straight lines.

A semiconductor memory device comprising:

• a semiconductor substrate including a plurality of active regions, a plurality of word line structures passing over the active regions, source and drain regions on the active regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions;
• an interlevel insulating layer on the semiconductor substrate;
• etch stoppers on the interlevel insulating layer;
• storage node contact plugs in the interlevel insulating layer and the etch stoppers;
• storage node electrodes, which comprise a plurality of conductive line patterns separated in the same intervals while having a specific height, contacting the storage node contact plugs;
• and
• supporters between the storage node electrodes and extending perpendicular to an extending direction of the line patterns of the storage node electrodes;
• wherein, the plurality of line patterns comprise waves in a plan view.

A method of manufacturing a semiconductor memory device, the method comprising:

• depositing an interlevel insulating layer on a semiconductor substrate;
• forming a plurality of storage node contact plugs in the interlevel insulating layer in specific intervals;
• forming mold oxide layer patterns on the interlevel insulating layer in specific intervals to expose the storage node contact plugs;
• filling the spaces between the mold oxide layer patterns by alternately forming conductive line patterns and insulating line patterns, repeatedly, on sidewalls of the mold oxide layer patterns;
• forming grooves perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns;
• and
• forming storage node electrodes by selectively removing the mold oxide layer patterns and the insulating line patterns.

A method for manufacturing a semiconductor memory device, the method comprising:

• preparing a semiconductor substrate including a plurality of active regions, a plurality of word line structures passing over the active regions, source and drain regions formed on the active regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions;
• forming an interlevel insulating layer on the semiconductor substrate;
• forming etch stoppers on the interlevel insulating layer;
• forming storage node contact plugs in the interlevel insulating layer and the etch stoppers at specific intervals;
• forming a plurality of mold oxide layer patterns on the etch stoppers at specific intervals to expose the storage node contact plugs;
• filling spaces between the mold oxide layer patterns by alternately forming at least one conductive line pattern and insulating line pattern on the sidewalls of the mold oxide layer patterns in order to follow the shape of the mold oxide layer patterns;
• forming grooves substantially perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns;
• forming supporters in the grooves;
• and
• forming storage node electrodes by selectively removing the mold oxide layer patterns and the insulating line patterns;
• wherein the mold oxide layer patterns extend into straight lines and the mold oxide layer patterns and the supporters separate the storage node electrodes in units of each cell.

A method for manufacturing a semiconductor memory device, the method comprising:

• preparing a semiconductor substrate including a plurality of active regions, a plurality of word line structures passing over the active regions, source and drain regions formed on the active regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions;
• forming an interlevel insulating layer on the semiconductor substrate;
• forming etch stoppers on the interlevel insulating layer;
• forming storage node contact plugs in the interlevel insulating layer and the etch stoppers at specific intervals;
• forming a plurality of mold oxide layer patterns, which are formed in the shape of waves in a plan view, on the etch stoppers to expose the storage node contact plugs;
• filling spaces between the mold oxide layer patterns by alternately forming at least one conductive line pattern and insulating line pattern on the sidewalls of the mold oxide layer patterns in order to follow the shape of the mold oxide layer patterns;
• forming grooves substantially perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns;
• forming supporters in the grooves;
• and
• forming storage node electrodes by selectively removing the mold oxide layer patterns and the insulating line patterns;
• wherein the mold oxide layer patterns and the supporters separate the storage node electrodes in units of each cell.

A storage node for a semiconductor memory device comprising:

• a pair of spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facing mold oxide layer pattern sidewalls;
• a pair of first conductive spacers, a respective one of which is on a respective one of the facing mold oxide layer pattern sidewalls and face one another;
• a pair of first insulating spacers, a respective one of which is on a respective one of the pair of first conductive spacers, opposite the respective one of the facing mold oxide layer pattern sidewalls;
• a pair of second conductive spacers, a respective one of which is on a respective one of the pair of first insulating spacers, opposite the respective one of the pair of first conductive spacers;
• and
• at least one second insulating spacer between the pair of second conductive spacers.

A method of fabricating a storage node for a semiconductor memory device comprising:

• forming spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facing mold oxide layer pattern sidewalls;
• forming a first conductive spacer on each of the facing mold oxide layer pattern sidewalls;
• forming a first insulating spacer on each of the first conductive spacers, opposite the respective one of the facing mold oxide pattern sidewalls;
• forming a second conductive spacer on each of the first insulating spacers, opposite the respective one of the pair of first conductive spacers;
• and
• forming at least one second insulating spacer between the pair of second conductive spacers.