Semiconductor device
AssigneeRenesas Technology Corp.
InventorsToru Fujioka, Isao Yoshida, Toshihiko Shimizu
Life of this patent
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AssigneeRenesas Technology Corp.
InventorsToru Fujioka, Isao Yoshida, Toshihiko Shimizu
Estimating the term…
It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.
A semiconductor device in which a semiconductor amplifying element is formed, and electrodes for inputting and electrodes for outputting electrically connected to said semiconductor amplifying element are provided on its surface,
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device provided with:
Dependencies are inferred from the claim text.