Process for creating holes in polymeric substrates
AssigneePPG Industries Ohio, Inc.
InventorsKevin C. Olson, Alan E. Wang
Life of this patent
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Abstract
Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.
Claims47
A process for creating a via through a substrate comprising the following steps:
- (a) providing a substantially void-free curable film comprised of a curable composition;
- (b) applying a resist onto said curable film;
- (c) imaging said resist in predetermined locations;
- (d) developing said resist to expose predetermined areas of the curable film;
- (e) removing the exposed areas of the curable film to form holes through said curable film;
- and
- (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition.
A process for fabricating a multi-layer electrical circuit assembly comprising the following steps:
- (a) providing a substantially void-free curable film of a curable composition;
- (b) applying a resist onto said curable film;
- (c) imaging said resist in predetermined locations;
- (d) developing said resist to expose predetermined areas of the curable film;
- (e) removing the exposed areas of the curable film to form holes through said curable film;
- (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition;
- (g) stripping the remaining resist;
- (h) applying a layer of metal to all surfaces;
- (i) applying a second resist over all surfaces of the layer of metal applied in step (h);
- (j) imaging and developing said second resist to reveal a predetermined pattern of uncovered underlying metal;
- (k) etching said uncovered portions of the underlying layer of metal;
- (l) stripping the remaining second resist to form an electrical circuit pattern.
- (m) applying a dielectric composition to all surfaces;
- (n) providing vias in said dielectric composition in predetermined locations;
- (o) applying a second layer of metal to all surfaces;
- (p) applying a third resist to all surfaces of said second layer of metal;
- (q) imaging and developing said third resist to expose a predetermined pattern of the second layer of metal;
- (r) etching said exposed portions of the second layer of metal to form an electrical circuit pattern;
- (s) stripping the remaining third resist;
- and
- (t) optionally repeating steps (n) through (t) one or more times to form multiple layers of interconnecting electrical circuit patterns.
A process for creating a via through a substrate comprising the following steps:
- (a) providing a substantially void-free film;
- (b) applying a resist onto said film;
- (c) imaging said resist in predetermined locations;
- (d) developing said resist to expose predetermined areas of the film;
- and
- (e) removing the exposed areas of the film to form holes through said film;
Dependencies are inferred from the claim text.