Isolation chamber arrangement for serial processing of semiconductor wafers for the electronic industry

A method of preparing semiconductor wafers, comprising:

• arranging a stationary upper platen and a stationary lower plate on a frame, with said upper platen having a plurality of upper housings spaced circumferentially therearound, and said lower plate having a corresponding plurality of lower housings spaced circumferentially therearound;
• rotatively supporting an indexable plate between said upper platen and said lower plate;
• loading a wafer to be treated onto an arrangement of support pins extending at least part way across said opening on said indexable plate;
• rotating said indexable plate between said upper platen and said lower plate for successive treatment process locations for treatment of said wafer;
• and
• isolating said wafer on said index plate at each treatment location for independent controlled access and treatment of said wafer thereat.

A method of preparing semiconductors, comprising:

• rotating a wafer bearing indexing plate into alignment between an upper housing on a stationary upper platen and a lower housing on a stationary lower plate;
• lifting a treatment plate into supportive engagement with said wafer borne by said indexing plate;
• and
• isolating said wafer to provide an individual sealed containment thereof during a treatment process applied to said wafer.