Non-intrusive signal observation techniques usable for real-time internal signal capture for an electronic module or integrated circuit
OwnerKushagra V. Vaid, Piyush Desai +1inventors
InventorsKushagra V. Vaid, Piyush Desai, Victor W. Lee
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Abstract
Internal bus observation techniques for an electronic module or integrated circuit. In one embodiment, a disclosed apparatus includes observation logic to observe an observed bus and a debug buffer. The observation logic captures a record reflecting signal observed on the observed bus. The debug buffer is coupled to the observation logic to receive the record that reflects signal observed by the observation logic. The debug buffer generates a transaction to transfer the record to a storage device to store the record.
Claims42
An apparatus comprising:
- an observed bus;
- observation logic operative in a test mode to capture a plurality of records that reflect a sequence of signals on said observed bus as said sequence of signals occurs;
- preservation logic to cause preservation of said plurality of records within a system memory.
A system comprising:
- a system memory to store processor instructions in a first mode and to store trace sequences in a second mode;
- a first node comprising a processor, a memory interface, an interface, and observation logic to capture an internal transaction sequence from information internal to said first node and to stream said internal transaction sequence to the system memory via said interface.
A method comprising:
- capturing a sequence of bus transactions on an internal bus as the sequence of bus transactions occurs;
- preserving said sequence of bus transactions in a system storage device.
An apparatus comprising:
- a first sub-component;
- a second sub-component;
- a plurality of signal lines to couple said first sub-component and said second sub-component;
- observation logic to capture a sequence of signals on said plurality of signal lines and to generate a representation of said sequence of signals having a reduced number of bits used to represent said sequence of signals;
- preservation logic couple to said observation logic to store said representation of said sequence of signals in a system memory.
An apparatus comprising:
- means for observing a sequence of signals on a plurality of signal lines;
- a system memory means for storing system data usable in normal operations;
- means for storing said sequence of signals in said system memory means.
Dependencies are inferred from the claim text.