Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems
AssigneeMediatek Inc.
InventorChang-Fu Lin
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Abstract
In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetching device is also disclosed.
Claims7
A method for fetching instructions in an embedded system that includes a system bus, a processor coupled to the system bus, a peripheral controller coupled to the system bus, and a memory device having a set of the instructions stored therein, said method comprising the steps of:
- a) determining whether the system bus is mastered by the peripheral controller;
- b) fetching a predicted one of the instructions from the memory device, and storing the predicted one of the instructions in an instruction buffer when the system bus is mastered by the peripheral controller;
- c) determining whether the processor generates an access request for the memory device;
- d) determining whether the predicted one of the instructions stored in the instruction buffer hits the access request from the processor upon determining that the processor generated the access request;
- and
- e) providing the predicted one of the instructions stored in the instruction buffer to the system bus for receipt by the processor when the predicted one of the instructions stored in the instruction buffer hits the access request from the processor.
An embedded system comprising:
- a system bus for signaling and data transactions;
- a processor coupled to said system bus;
- a peripheral controller coupled to said system bus;
- a memory device having a set of instructions stored therein;
- and
- an instruction prefetching device coupled to said system bus and said memory device, said instruction prefetching device monitoring transaction on said system bus and fetching a predicted one of the instructions from said memory device when said system bus is mastered by said peripheral controller, said instruction prefetching device receiving an access request for said memory device from said processor through said system bus, and providing the predicted one of the instructions to said system bus for receipt by said processor when the predicted one of the instructions hits the access request from said processor.
An instruction prefetching device adapted for use in an embedded system that includes a system bus, a processor coupled to the system bus, a peripheral controller coupled to the system bus, and a memory device having a set of instructions stored therein, said instruction prefetching device comprising:
- a prefetching controller adapted to coupled to the system bus and adapted to monitor signal transaction on the system bus;
- a memory controller coupled to said prefetching controller and adapted to be coupled to the memory device;
- and
- an instruction buffer coupled to said prefetching controller and said memory controller;
- said prefetching controller enabling said memory controller to fetch a predicted one of the instructions from the memory device and to store the predicted one of the instructions in said instruction buffer when said prefetching controller determines that the system bus is mastered by the peripheral controller;
- said prefetching controller being adapted to receive an access request for the memory device from the processor through the system bus when the system bus is not mastered by the peripheral controller, and being adapted to provide the predicted one of the instructions stored in said instruction buffer to the processor through the system bus when the predicted one of the instructions stored in said instruction buffer hits the access request from the processor.
Dependencies are inferred from the claim text.