Enhanced instruction prefetch engine

An information processing system comprising:

• a processor comprising an instruction execution unit for executing instructions and a prefetch unit for prefetching instructions;
• a slower memory, coupled to the processor, for storing instructions;
• and
• a faster memory, coupled to the processor;
• wherein the prefetch unit is configured to perform the following:
• prefetching instructions from the slower memory;
• recognizing, a prefetched instruction as being a conditional branch instruction;
• prefetching instructions along each of the possible branches for the conditional branch instruction, responsive to recognizing the opcode corresponding to the conditional branch instruction;
• and canceling prefetching of instructions from branches not taken by the execution unit.

A machine readable medium comprising program instructions for:

• prefetching instructions from a slower memory for storing in a faster memory;
• recognizing a prefetched instruction, as being a conditional branch instruction;
• prefetching instructions along each of the possible branches for the conditional branch instruction, responsive to recognizing the conditional branch instruction;
• executing instructions from a branch from among the possible branches of the conditional branch;
• and
• canceling prefetching of instructions from other branches not being executed by the execution unit.

An information processing device comprising:

• an instruction execution unit for executing instructions;
• a prefetch unit for prefetching instructions;
• and an instruction cache for storing instructions from a slower system memory;
• wherein the prefetch unit comprises circuitry for:
• prefetching instructions from the slower memory;
• recognizing, a prefetched instruction as being a conditional branch instruction;
• prefetching instructions along each of the possible branches for the conditional branch instruction, responsive to recognizing the opcode corresponding to the conditional branch instruction;
• and
• the execution unit comprises circuitry for canceling prefetching of instructions from branches not executed.