US 2003/0233384 A1 · Arithmetic apparatus for performing high speed multiplication and addition operations

Abstract

An arithmetic unit that performs high speed multiplication and addition operations is provided. The arithmetic unit is applicable to an instruction set not having a multiplication-addition instruction. The arithmetic circuit included in a data processing device is configured to have: a multiplication device (EMUL1) to which data A and B are inputted and which outputs partial signals, sum signal (113) and carry signal (114), for computing A*B; a first addition device (EADD1) which adds the sum signal and the carry signal to compute the final result of A*B; and a second addition device (EADD2) which receives data E, the sum signal, and the carry signal and is capable of computing the result of adding E to A*B. The arithmetic circuit selects among three types of operations, multiplication (A*B), addition (D+E), and multiplication-addition (A*B+E) by selection circuits 104 and 105.

Claims17

Dependent claims

A data processing device including an arithmetic circuit, wherein the arithmetic circuit comprises:

a first input node configured to receive first data;
a second input node configured to receive second data;
a multiplication device configured to receive the first and second data and to output a sum signal and a carry signal, which are partial signals for computing a product between the first and second data;
a first addition device configured to add the sum signal and the carry signal to compute the result of the product between the first and second data;
a first output node configured to output a computation result of the first addition device;
a third input node configured to receive third data;
a second addition device configured to receive the third data, the sum signal, and the carry signal, and further configured to add the third data to a product between the first and the second data;
and
a second output node configured to output a computation result of the second addition device.

6 more elements

A data processing device having an arithmetic circuit, wherein the arithmetic circuit comprises:

a first input node configured to receive first data;
a second input node configured to receive second data;
a multiplication device configured to receive the first and the second data and to output a sum signal and a carry signal, which are partial signals for computing a product between the first and the second data;
a first addition device configured to add the sum signal and the carry signal to compute the result of the product between the first and the second data;
a first output node configured to output a computation result of the first addition device;
a third input node configured to receive third data;
a fourth input node configured to receive fourth data;
a second addition device;
and
a second output node configured to output a computation result of the second addition device, wherein the second addition device is configured to switch between the operation of adding the third data, the sum signal, and the carry signal, and the operation of adding the third data and the fourth data.

7 more elements

Dependencies are inferred from the claim text.

Arithmetic apparatus for performing high speed multiplication and addition operations

Life of this patent

Arithmetic apparatus for performing high speed multiplication and addition operations

Life of this patent

Abstract

Claims17