Method of forming a system on chip

A method of forming a system on chip (SOC), the method utilizing nitride read only memory (NROM) to establish read only memory (ROM) and non-volatile memory, a substrate of the system on chip comprising a memory area and a periphery area, the memory area further comprising a non-volatile memory area and a read only memory area, the read only memory area further comprising at least a low threshold voltage (low Vth) device area and a high threshold voltage (high Vth) device area, the method comprising:

• forming a plurality of field oxide layers on the surface of the substrate so as to form an isolator of each device in the periphery area, the non-volatile memory area, and the read only memory area, respectively, and to define the active area of each device;
• forming an ONO dielectric layer on the surface of the substrate, the ONO dielectric layer comprising a bottom oxide layer, a silicon nitride layer, and a top oxide layer;
• forming a first photoresist layer on the surface of the ONO dielectric layer, and performing a first lithography process so as to define sites for a plurality of bit lines;
• performing a first etching process, the first etching process utilizing the first photoresist layer as a mask so as to remove the top oxide layer and the silicon nitride layer and part of the bottom oxide layer not covered by the first photoresist layer;
• performing a first ion implantation process so as to form a plurality of N-type doping areas, and each of the buried bit lines in the memory area;
• removing the first photoresist layer;
• performing a thermal oxidation process so as to form a buried drain oxide layer atop the surface of each buried bit line;
• forming first a polysilicon layer and then a second photoresist layer on the surface of the substrate so as to define sites of a plurality of word lines in the memory area and a plurality of gates in the periphery area in the second photoresist layer by utilizing a second lithography process;
• performing a second etching process to simultaneously remove the polysilicon layer not covered by the second photoresist layer and form each of the word lines in the memory area and each gate of the periphery transistor in the periphery area, so as to form at least one NROM in the non-volatile memory area, a low threshold voltage(low Vth) device in the low threshold voltage device area of the read only memory area, and a high threshold voltage(high Vth) device in the high threshold voltage device area in the read only memory area;
• and
• removing the second photoresist layer.