Process and system for repeater insertion in an IC design
AssigneeAgilent Technologies, Inc.
InventorPaul Douglas Nuber
Life of this patent
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Abstract
A method of generating an IC design comprises the steps of generating an intermediate routing result to define interconnects between functional blocks on an IC. The next step is defining one or more repeater ranches in an interstice of the IC and generating a repeater placement plan for placement of repeater elements according to the repeater ranch boundary constraints. The process continues with the step of generating a final routing result to define interconnects between functional blocks that interconnect the repeater elements according to the repeater placement plan.
Claims30
A method of generating an IC design comprising the steps of:
- generating an intermediate routing result to define interconnects between functional blocks on an IC,
- defining one or more repeater ranches in an interstice of said IC,
- generating a repeater placement plan for placement of repeater elements according to constraints of said repeater ranch boundaries, and
- generating a final routing result to define interconnects between functional blocks that interconnect said repeater elements according to said repeater placement plan.
A system for designing an IC comprising:
- a processing element,
- means for generating an intermediate routing result on said processing element to define interconnects between functional blocks on an IC,
- means for defining one or more repeater ranches in an interstice of said IC,
- means for generating a repeater placement plan on said processing element for placement of repeater elements according to constraints of said repeater ranches, and
- means for generating a final routing result on said processing element to define interconnects between functional blocks that interconnect the elements according to said repeater placement plan.
A method of positioning electronic repeater elements in an IC design comprising the steps of:
- executing a router process to position electrical interconnects between functional blocks for the IC design to generate an intermediate routing result,
- defining one or more repeater ranch boundaries in an interstice of the IC design, said repeater ranch boundaries defining exclusive placement areas for one or more repeater elements,
- executing a repeater insertion process according to said one or more repeater ranch boundaries to generate a repeater placement plan which defines positioning of repeater elements in said IC design,
- discarding said intermediate routing result,
- executing said router process with benefit of said repeater placement plan to generate a second routing result to interconnect said repeater elements of said repeater placement plan.
A system for positioning electronic repeater elements in an IC design comprising:
- a processing device having access to memory,
- a graphical display device in communication with said processing device,
- means for executing a routing process on said processing device to define positions for electrical interconnects between functional blocks for the IC design to generate an intermediate routing result,
- means for defining on said graphical display device one or more repeater ranch boundaries in an interstice of the IC design, said repeater ranch boundaries defining exclusive placement areas for one or more repeater elements,
- means for executing a repeater insertion process on said processing device to generate a repeater placement plan consistent with constraints of said one or more repeater ranch boundaries to define positions of repeater elements in said IC design, and
- means for executing said routing process on said processing device with benefit of said repeater placement plan to generate a final routing result to interconnect said repeater elements of said repeater placement plan.
Dependencies are inferred from the claim text.