Method and apparatus to facilitate global routing for an integrated circuit layout

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for generating a global routing for a layout of an integrated circuit, comprising

• receiving a netlist to be routed;
• partitioning the netlist into global signals, datapath signals, and control signals;
• creating a first tiling grid of the integrated circuit;
• routing connection nets within the first tiling grid, wherein connection nets are routed between tiles on the first tiling grid;
• selecting a target area within the integrated circuit, wherein the target area includes a portion of the integrated circuit that is larger than a tile in the first tiling grid;
• creating a second tiling grid in the target area, wherein tiles of the second tiling grid are smaller than tiles of the first tiling grid;
• routing connection nets within the target area, wherein connection nets are routed between tiles on the second tiling grid, and wherein routings within the first tiling grid are maintained;
• and
• merging connection nets within the first tiling grid with connection nets within the second tiling grid to form the global routing, whereby merging the first tiling grid and the second tiling grid allows more accurate routing in the target area.

An apparatus for generating a global routing for a layout of an integrated circuit, comprising

• a receiving mechanism that is configured to receive a netlist to be routed;
• a partitioning mechanism that is configured to partition the netlist into global signals, datapath signals, and control signals;
• a creating mechanism that is configured to create a first tiling grid of the integrated circuit;
• a routing mechanism that is configured to route connection nets within the first tiling grid, wherein connection nets are routed between tiles on the first tiling grid;
• a selecting mechanism that is configured to select a target area within the integrated circuit, wherein the target area includes a portion of the integrated circuit that is larger than a tile in the first tiling grid;
• wherein the creating mechanism is further configured to create a second tiling grid in the target area, wherein tiles of the second tiling grid are smaller than tiles of the first tiling grid;
• wherein the routing mechanism is further configured to route connection nets within the target area, wherein connection nets are routed between tiles on the second tiling grid, and wherein routings within the first tiling grid are maintained;
• and
• a merging mechanism that is configured to merge connection nets within the first tiling grid with connection nets within the second tiling grid to form the global routing, whereby merging connection nets within the first tiling grid and connection nets within the second tiling grid allows more accurate routing in the target area.