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US 2003/0229875 A1Published application
Use of models in integrated circuit fabrication
OwnerTaber H. Smith, Vikas Mehrotra +1inventors
InventorsTaber H. Smith, Vikas Mehrotra, David White
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Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Claims108
A method comprising
- performing pattern dependent modeling and prediction for electrochemical mechanical deposition, chemical vapor deposition of low-K interlayer dielectric, or spin-on of low-K interlayer dielectric.
A method comprising
- based on electrical impact analysis and a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and
- using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,
- the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy.
A method comprising
- based on an electrical impact analysis and a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and
- using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,
- the fabrication process for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.
A method comprising
- based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and
- using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,
- the fabrication process for which the strategy is being generated comprising two or more stages of fabrication.
A method comprising
- based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and
- using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,
- the fabrication process for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.
A method comprising
- operating a server to provide dummy fill generation functions for a semiconductor design, and
- enabling a user at a client to operate through a web browser to use the dummy fill placement functions.
A method comprising
- using a pattern dependent model to analyze an integrated circuit design,
- applying a dummy fill strategy to the design
- analyzing the design to which the dummy fill strategy has been applied,
- adjusting the design based on the analysis,
- iterating the analyzing and adjusting steps, and
- certifying that that a integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.
3 more elements
A method comprising
- defining a set of hierarchical cell placements for dummy fill for a semiconductor fabrication process, and
- reducing a size of an electronic layout file to which dummy fill is added by using the hierarchical cell placements.
A method comprising
- using patterned test wafers or test semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe, and
- based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process.
A method comprising
- generating full-chip pattern dependent models for at least one of the following processes:
- electrochemical deposition, electrochemical mechanical deposition, copper chemical mechanical polishing, lithography, shallow trench isolation chemical mechanical polishing, chemical vapor deposition low-K interlayer dielectric, spin-on low-K interlayer dielectric, and
- based on the pattern dependent model, generating a strategy for placement of dummy fill in the process.
A method comprising
- using a calibrated pattern dependent model to map pattern dependent features to wafer-state parameters such as resulting film thickness, film thickness variation, dishing, erosion and electrical parameters such as sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant, and
- based on the pattern dependent model, generating a strategy for placement of dummy fill in a fabrication process.
A method comprising
- based on a pattern dependent model, generating a strategy for placement of dummy fill in a process, and
- using a cost function to measure an impact of dummy fill modification on process induced wafer state and electrical parameter variation.
A method comprising
- based on a combination of more than one pattern dependent model, generating a strategy for placement of dummy fill in a process, and
- predicting an impact of the dummy fill generated by the strategy on process variation.
A method comprising
- based on a combination of more than one pattern dependent model and cost function, generating a strategy for placement of dummy fill in a process that optimizes full-chip wafer-state and electrical parameters
A method comprising
- based on predicted or simulated wafer state and electrical parameters, generating dummy fill rules for use in dummy fill placement in a semiconductor fabrication process.
A method comprising
- providing dummy fill functions to generate dummy fill for a semiconductor fabrication process, and
- using the functions to automatically modify GDS-format electronic layout files for a semiconductor device.
A method comprising
- at a server, receiving from a client layout file for a semiconductor device,
- generating dummy fill modifications to the layout file at the server, and
- returning the dummy fill modified layout file from the server to the client.
A method comprising
- at a web server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and
- enabling the user to generate dummy fill information using the dummy fill application.
A method comprising
- making available to a user on a network a service that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.
A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising sizes of dummy fill objects to be included in semiconductor device designs.
A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising libraries of dummy fill objects or patterns.
A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising libraries of dummy fill rules.
A method comprising
- maintaining a library of semiconductor dummy fill information, and
- making the library available for use in connection with generating dummy fill placement specifications, and
- updating the library with changed dummy fill information.
A method comprising
- storing calibration information with respect to at least one of the following:
- process tools, recipes, and flows, and
- updating the calibration information to reflect changes in the process tools, recipes or flows.
A method comprising
- enabling a user to obtain a dummy fill strategy for a semiconductor design using a single click of a user interface device through a user interface.
Dependencies are inferred from the claim text.