Method of generating timing constraint model of logic circuit, program for generating timing constraint model of logic circuit, and timing-driven layout method of using the timing constraint model

A method of generating a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths, the method comprising:

• reading a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• extracting, based on the static timing analyzer script, paths that do not have the disconnection information;
• calculating a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• preparing, based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information.

A computer program which generates a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths on a computer, the computer program making the computer execute:

• reading a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• extracting, based on the static timing analyzer script, paths that do not have the disconnection information;
• calculating a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• preparing, based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information.

A timing-driven layout method comprising:

• generating a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths, the step of generating including
• reading a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• extracting, based on the static timing analyzer script, paths that do not have the disconnection information;
• calculating a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• preparing, based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information;
• analyzing the delay characteristic of the logic circuit under the timing constraints described in the compatible constraint set based on the compatible constraint set prepared;
• optimizing a delay in the logic circuit based on the timing constraints described in the compatible constraint set;
• and
• optimizing placement and route of a layout of the logic circuit based on the timing constraints described in the compatible constraint set.

A computer program that makes a computer execute:

• generating a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths, the step of generating including
• reading a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• extracting, based on the static timing analyzer script, paths that do not have the disconnection information;
• calculating a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• preparing, based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information;
• analyzing the delay characteristic of the logic under the timing constraints described in the compatible constraint set;
• optimizing the delay in the logic circuit based on the timing constraints described in the compatible constraint set;
• and
• optimizing placement and route of a layout of the logic circuit based on the timing constraints described in the compatible constraint set.

An apparatus that generates a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths, the apparatus comprising:

• an STA input unit that reads a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• a calculating unit that extracts, based on the static timing analyzer script, paths that do not have the disconnection information, and calculates a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• a preparing unit that prepares based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information.

A timing-driven layout system, comprising:

• a generating unit that generates a timing constraint model of a logic circuit that has one of a cell and an I/O terminal as a starting point and one of the cell and the I/O terminal as an ending point for each of a plurality of paths, the generating unit including
• an STA input unit that reads a static timing analyzer script that describes a clock information and a disconnection information, the clock information being supplied to the logical circuit, and the disconnection information indicating which path is to be disconnected from among the plurality of paths;
• a calculating unit that extracts, based on the static timing analyzer script, paths that do not have the disconnection information, and calculates a permissible delay time from the starting point to the ending point of each path extracted based on the clock information;
• and
• a preparing unit that prepares based on the calculated permissible delay time, which is equivalent to a time constraint of the extracted paths, and the disconnection information, a timing constraint model, which is equivalent to a compatible constraint set, for a plurality of groups in such a manner as to have no contradiction between the paths extracted and the disconnection information;
• an analyzing unit that analyzes the delay characteristic of the logic circuit under the timing constraints described in the compatible constraint set;
• a logic optimizing unit that optimizes the delay in the logic circuit based on one of all and a part of the timing constraints described in the prepared compatible constraint set;
• a compatible constraint set input unit that assigns the description in the compatible constraint set to be optimized;
• and
• a placing/routing optimizing unit that optimizes placement and route of a layout of the logic circuit based on the timing constraints described in the compatible constraint set.