Method and apparatus for providing a preselected voltage to test or repair a semiconductor device

An apparatus, comprising:

• a first and a second transistor adapted to access a first voltage;
• a first logic gate adapted to provide a second clock signal to a first capacitor using a first clock signal and an enable signal;
• a second logic gate adapted to provide a third clock signal to a second capacitor using the second clock signal and the enable signal, wherein the third clock signal is substantially inverted relative to the second clock signal;
• a first node between the first capacitor and the first transistor, wherein the first node is coupled to a gate of the second transistor;
• a second node between the second capacitor and the second transistor, wherein the second node is coupled to a gate of the first transistor;
• a first transfer device adapted to provide a second voltage using a third voltage provided to the second node by the first and second capacitors and the first and second transistors;
• and
• a second transfer device coupled to the first transfer device, wherein the second transfer device is capable of providing the first voltage to a third node using the second voltage.

A method, comprising:

• providing a first voltage to a one-stage pump;
• providing a second voltage to a first transfer device using the one-stage pump;
• and
• providing the first voltage to a node coupled to the first transfer device using the second voltage.

An apparatus, comprising:

• means for providing a first voltage to a one-stage pump;
• means for providing a second voltage using the first voltage supplied to the one-stage pump, wherein the second voltage is larger than the first voltage;
• and
• means for providing the first voltage to a node using the second voltage.

The apparatus of claim 32, wherein the means for providing the first clock signal and the second clock signal comprises:

• means for providing an enable signal;
• means for providing a third clock signal;
• means for providing the first clock signal to the one-stage pump using the third clock signal and the enable signal;
• and
• means for providing the second clock signal to the one-stage pump using the clock signal and the enable signal.

A system, comprising:

• a power supply capable of providing a first voltage;
• a clock capable of providing a first clock signal;
• a margin mode circuit coupled to the power supply and the clock, wherein the margin mode circuit is adapted to provide the first voltage to a test device using the clock signal;
• and
• a controller coupled to the margin mode circuit, wherein the controller is adapted to detect a current produced in the margin mode circuit by the test device in response to the first voltage.

An apparatus in a memory circuit for testing a semiconductor memory array, comprising:

• a power supply adapted to provide a first and a second voltage, wherein the first voltage is larger than the second voltage;
• a clock generator adapted to provide a first clock signal;
• a controller adapted to provide an enable signal;
• a margin mode circuit coupled to the power supply, the clock, and the controller, wherein the margin mode circuit is adapted to provide the first voltage to a test device using the clock signal and the second voltage in response to receiving the enable signal;
• and
• a detector coupled to the margin mode circuit, wherein the detector is adapted to detect a current produced in the margin mode circuit by the semiconductor memory array in response to the first voltage.

An apparatus in a memory circuit for testing a semiconductor memory array, comprising:

• an enable logic coupled to a first pad, wherein the enable logic is adapted to access a first voltage provided by the first pad and provide at least one of an enable signal and a disable signal in response to the first voltage;
• a clock generator coupled to a second pad, a third pad, and the enable logic, wherein the clock generator is adapted to provide a clock signal in response to detecting the enable signal using a signal provided by the second pad and a second voltage provided by the third pad;
• a one-stage pump coupled to a fourth pad and the clock generator, wherein the one-stage pump is adapted to provide a fourth voltage using the clock signal and a third voltage provided by the fourth pad;
• a transfer device coupled to the fourth pad, the one-stage pump, and the semiconductor memory array, wherein the transfer device is adapted to provide the third voltage to the semiconductor memory array using the fourth voltage.