Pad connection structure of embedded memory devices and related memory testing method
AssigneeSamsung Electronics Co., Ltd.
InventorSoon-Keun Jeon
Life of this patent
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Abstract
In a pad connection structure for a plurality of embedded memory devices in a system-on-a-chip configuration, common pads are separately allotted to signal lines of embedded memory devices used for identical purposes and corresponding multiplexers are connected between the common pads and the signal lines of the embedded memory devices, thereby significantly reducing the number of input and output pads of the memory merged logic, minimizing damage to the pads, as a result of low probing frequency, and sequentially testing the embedded memory devices in a single testing operation.
Claims7
A pad configuration, comprising
- a plurality of memory devices on a common integrated circuit, each memory device having at least one signal line of a similar purpose with at least one signal line of the other memory devices;
- and
- a multiplexer, for selectively coupling one of the respective signal lines to a common pad, in response to a signal line selection signal.
A method for testing a plurality of embedded memory devices on a common integrated circuit, the method comprising the steps of:
- providing a plurality of memory devices on a common integrated circuit, each memory device having a signal line of a similar purpose with signal lines of the other memory devices;
- selectively coupling at multiplexers, the respective signal lines of a similar purpose to respective common pads in response to signal line selection signals;
- sequentially testing the embedded memory devices at the common pads to respectively record and repair defective addresses of the embedded memory devices in a single test operation.
Dependencies are inferred from the claim text.