Back to results
US 2003/0229828 A1Published application
Arrangements for self-measurement of I/O timing
AssigneeIntel Corporation
InventorsHarry Muljono, Alper Ilkbahar
Life of this patent
Estimating the term…
Abstract
Arrangements (circuits, methods, systems) having self-measurement of input/output (I/O) timing.
Claims30
A circuit comprising:
- an input/output loop-back (iolb) timing-locked-loop (TLL) clock circuit to generate at least a first iolb clock and a second iolb clock having a time-lockable relationship to one another for substantially time-locked iolb travel/capture of test data along at least one iolb path, such time-lockable relationship of the first iolb clock and the second iolb clock being selectably variable to a plurality of differing time-locked relationships to one another during iolb testing.
An electronic system comprising:
- at least one of system memory and a power supply;
- and
- a circuit having:
- an input/output loop-back (iolb) timing-locked-loop (TLL) clock circuit to generate at least a first iolb clock and a second iolb clock having a time-lockable relationship to one another for substantially time-locked iolb travel/capture of test data along at least one iolb path, such time-lockable relationship of the first iolb clock and the second iolb clock being selectably variable to a plurality of differing time-locked relationships to one another during iolb testing.
1 more element
A method comprising:
- generating, using an input/output loop-back (iolb) timing-locked-loop (TLL) clock circuit, at least a first iolb clock and a second iolb clock having a time-lockable relationship to one another for substantially time-locked iolb travel/capture of test data along at least one iolb path, such time-lockable relationship of the first iolb clock and the second iolb clock being selectably variable to a plurality of differing time-locked relationships to one another during iolb testing.
Dependencies are inferred from the claim text.