Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers

A method comprising:

• receiving memory request hints from a CPU coupled to a memory controller, the memory request hints being used by a prefetcher in the memory controller to perform prefetch operations to prefetch information from one or more memory devices coupled to the memory controller via a memory bus;
• determining the type of memory request hints provided by the CPU, the type of memory request hints being used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request;
• and
• generating prefetch requests to prefetch information from the one or more memory devices, based, at least in part, on the type of memory request hints provided by the CPU and bandwidth availability of the memory bus;

A system comprising:

• a central processing unit (CPU);
• and
• a memory controller coupled to the CPU, including:
• a prefetcher to prefetch information from one or more memory devices for use by the CPU, the prefetcher including:
• logic to receive memory request hints from the CPU, the memory request hints being used by the prefetcher in the memory controller to perform its corresponding prefetch operations;
• logic to determine the type of memory request hints provided by the CPU, the type of memory request hints being used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request;
• and
• logic to generate prefetch requests to prefetch information from the one or more memory devices, based, at least in part, on the type of memory request hints provided by the CPU and bandwidth availability of a memory bus connecting the memory controller with the one or more memory devices.

A system comprising:

• a processor including:
• a cache memory to store information for use by one or more execution units of the processor;
• a prefetch request buffer to store prefetch requests initiated by the CPU;
• and
• a stride analyzer to generate stride information associated with prefetch requests stored in the prefetch request buffer;
• a memory controller coupled to the processor, including:
• a buffer to store memory request information received from the CPU including memory request addresses and hints;
• and
• one or more memory devices coupled to the memory controller via a memory bus,
• wherein the memory controller performs prefetch operations based on the memory request hints received from the CPU and bandwidth availability of the memory bus.