DMA chaining method, apparatus and system
OwnerDavid Frank Hepner, Andrew Dale Wallsinventors
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Abstract
Related DMA transfers are chained by detecting a memory access to a selectable location corresponding to a first DMA transfer. A second DMA transfer may be initiated without CPU intervention in response to the detected memory access. Data transfers such as those related to data communications may be overlapped without waiting for reception of the entire communication. The present invention increases system throughput while reducing data latency and is particularly useful within systems that use intelligent peripherals or controllers. The architecture of the present invention permits deployment within existing systems using both chainable and conventional DMA devices.
Claims21
A method for chaining and overlapping DMA transfers, the method comprising:
- detecting a first DMA transfer;
- and
- conducting a second DMA transfer in response to the detected first DMA transfer.
A method for chaining and overlapping DMA transfers, the method comprising:
- detecting a memory access to a memory location corresponding to a first DMA transfer, the first DMA transfer comprising a plurality of write operations to sequential memory locations;
- and
- conducting a second DMA transfer comprising a plurality of read operations from the sequential memory locations in response to the detected memory access, the first and second DMA transfers conducted on separate DMA devices.
An apparatus for conducting overlapped and chained DMA transfers, the apparatus comprising:
- means for detecting a first DMA transfer;
- means for conducting a second DMA transfer in response to detection of the first DMA transfer.
An apparatus for conducting chained DMA transfers, the apparatus comprising:
- a DMA transfer detector configured to detect a first DMA transfer;
- and
- a DMA controller configured to conduct a second DMA transfer in response to detection of the first DMA transfer.
A system for conducting overlapping and chained DMA transfers, the system comprising:
- a memory configured to store data within a plurality of memory locations;
- a DMA detector configured to detect DMA transfers comprising at least one memory access to the memory and assert a chaining signal in response to detecting a selected DMA transfer;
- a DMA device configured to receive the chaining signal and conduct a subsequent overlapping DMA transfer in response to assertion of the chaining signal;
- and
- a CPU configured to set up DMA transfers on at least one DMA device.
Dependencies are inferred from the claim text.